L 1 "main.c"
N/*
NАвтор:	Дьячков Петр
NДата:	12.05.2011
NВерсия:	1.1
N
NПрограмма, реализующая ICMP-сервера на микроконтроллере 1986ВЕ91Т1 и Ethernet-контроллере 5600ВГ1У.
NИспользуется параллельный интерфейс.
N
N1986ВЕ91Т1: Частота тактирования микроконтроллера: 8 МГц.
N
N5600ВГ1У: MAC-адрес: 0A.1B.2C.3D.4E.5F
N          Прием широковещательных пакетов и с полным совпадением MAC-адреса
N
N          IP-адрес: 192.168.1.87
N          контроллер по ICMP-протоколу может принимать пакеты от 0 до 1472 байт
N		  фрагментированные пакеты не поддерживаются.
N*/
N
N#define NUMRXDESCRIPTOR	16	//количество дескрипротов принимаемых пакетов (минимум 1, максимум 32)
N#define NUMTXDESCRIPTOR	16	//количество дескрипротов отправляемых пакетов (минимум 1, максимум 32)
N
N#define PRINTSTATUSON	1	//компилляция программы с подключением отладочной информацией (1 - включено, 0 - отключено)
N
N//Структура для дескриптора принимаемых пакетов
Ntypedef struct
N{
N	unsigned int	StartAddress;			//начальный адрес дескриптора в памяти контроллера 1986ВЕ91Т1
N	unsigned short	Status;					//стату дескриптора
N	unsigned short	PacketLength;			//длина принятого пакета
N	unsigned short	PacketStartAddressH;	//адрес в буфере, где расположен первый байт пакета (старшая часть, всегда 0х0000)
N	unsigned short	PacketStartAddressL;	//адрес в буфере, где расположен первый байт пакета (младшая часть)
N	unsigned short	LastDesc;				//признак последнего дескриптора (1 - последний дескриптор, 0 - не последний дескриптор)
N} _rx_descriptor;
N
N//Структура для работы с текущим дескриптором принимаемых пакетов
Ntypedef struct
N{
N	_rx_descriptor* RxCurrentDescriptor;	//указатель на текущий дескриптор принимаемых пакетов
N	unsigned short Number;					//номер текущего дескриптора (принимает значения от 0 до NUMRXDESCRIPTOR-1)
N} _rx_current_descriptor;
N
N//Структура для дескриптора отправляемых пакетов
Ntypedef struct
N{
N	unsigned int	StartAddress;			//начальный адрес дескриптора в памяти контроллера 1986ВЕ91Т1
N	unsigned short	Status;					//стату дескриптора
N	unsigned short	PacketLength;			//длина принятого пакета
N	unsigned short	PacketStartAddressH;	//адрес в буфере, где расположен первый байт пакета (старшая часть, всегда 0х0000)
N	unsigned short	PacketStartAddressL;	//адрес в буфере, где расположен первый байт пакета (младшая часть)
N	unsigned short	LastDesc;				//признак последнего дескриптора (1 - последний дескриптор, 0 - не последний дескриптор)
N} _tx_descriptor;
N
N//Структура для работы с текущим дескриптором отпарвляемых пакетов
Ntypedef struct
N{
N	_tx_descriptor* TxCurrentDescriptor;	//указатель на текущий дескриптор отправляемых пакетов
N	unsigned short Number;					//номер текущего дескриптора (принимает значения от 0 до NUMTXDESCRIPTOR-1)
N	unsigned int FirstEmptyWord;			//адрес первого свободного слова в буфере передатчика
N} _tx_current_descriptor;
N
N#include "config.h"
L 1 "config.h" 1
N#ifndef __CONFIG_H_
N#define __CONFIG_H_
N
N//Управляющие регистры Ethernrt-контроллера 5600ВГ1У
Ntypedef struct
N{
N	unsigned int MAC_CTRL;
N    unsigned int MinFrame;
N    unsigned int MaxFrame;
N    unsigned int CollConfig;
N    unsigned int IPGTx;
N    unsigned int MAC_ADDR_T;
N    unsigned int MAC_ADDR_M;
N    unsigned int MAC_ADDR_H;
N    unsigned int HASH0;
N    unsigned int HASH1;
N    unsigned int HASH2;
N    unsigned int HASH3;
N    unsigned int INT_MSK;
N    unsigned int INT_SRC;
N    unsigned int PHY_CTRL;
N    unsigned int PHY_STAT;
N    unsigned int RXBF_HEAD;
N    unsigned int RXBF_TAIL;
N    unsigned int dammy0;
N    unsigned int dammy1;
N    unsigned int STAT_RX_ALL;
N    unsigned int STAT_RX_OK;
N    unsigned int STAT_RX_OVF;
N    unsigned int STAT_RX_LOST;
N    unsigned int STAT_TX_ALL;
N    unsigned int STAT_TX_OK;
N    unsigned int base_RxBF;
N    unsigned int base_TxBF;
N    unsigned int base_RxBD;
N    unsigned int base_TxBD;
N    unsigned int base_RG;
N    unsigned int GCTRL;
N} _ethernet;
N
N
N//Стартовый адрес буфера приемника
N#define BASE_ETH_RXBuffer                  0x60000000  //Absolut ADDRESS = 0x0000
N
N//Стартовый адрес буфера дескрипторов принимаемых пакетов
N#define BASE_ETH_RXDescBuffer              0x60002000  //Absolut ADDRESS = 0x0800
N
N//Стартовый адрес передатчика
N#define BASE_ETH_TXBuffer                  0x60004000  //Absolut ADDRESS = 0x1000
N
N//Стартовый адрес буфера дескрипторов передаваемых пакетов
N#define BASE_ETH_TXDescBuffer              0x60006000  //Absolut ADDRESS = 0x1800
N
N//Стартовый адрес управляющих регистров Ethernrt-контроллера 5600ВГ1У
N#define BASE_ETHERNET                      0x60007F00  //Absolut ADDRESS = 0x1FC0
N
N#define Ethernet              ((_ethernet *)BASE_ETHERNET)
N
N#define RxBuffer              ((unsigned int *)BASE_ETH_RXBuffer)
N#define RxDescriptor          ((unsigned int *)BASE_ETH_RXDescBuffer)
N
N#define TxBuffer              ((unsigned int *)BASE_ETH_TXBuffer)
N#define TxDescriptor          ((unsigned int *)BASE_ETH_TXDescBuffer)
N
N//#include "1986be91t1.h"
N#include "1901BC1F.h"
L 1 ".\inc\1901BC1F.h" 1
N/**
N  ******************************************************************************
N  * @file    1901BC1F.h
N  * @author  Phyton Application Team
N  * @version V1.0.0
N  * @date    14/01/2011
N  * @brief   This file contains all the Special Function Registers definitions
N  *          for the Milandr 1901BC1F microcontroller.
N  ******************************************************************************
N  * @copy
N  *
N  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
N  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
N  * TIME. AS A RESULT, PHYTON SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
N  * OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
N  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
N  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
N  *
N  * <h2><center>&copy; COPYRIGHT 2010 Phyton</center></h2>
N  ******************************************************************************
N  * FILE 1901BC1F.h
N  */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __1901BC1F_H
N#define __1901BC1F_H
N
N/** @addtogroup __CMSIS CMSIS
N  * @{
N  */
N
N/** @defgroup __1901BC1F 1901BC1F
N  * @{
N  */
N
N/** @defgroup __Exported_types Exported types
N  * @{
N  */
N
N/**
N  * @brief 1901BC1F Interrupt Number Definition
N  */
N
Ntypedef enum IRQn
N{
N/******  Cortex-M3 Processor Exceptions Numbers ***************************************************/
N  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                             */
N  HardFault_IRQn              = -13,    /*!< 3 Cortex-M3 Hard Fault Interrupt                     */
N  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt              */
N  BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                      */
N  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                    */
N  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                       */
N  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                       */
N  SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                   */
N
N/****** 1901BC1F specific Interrupt Numbers *******************************************************/
N  SSP3_IRQn                   = 0,      /*!< SPI3 Interrupt                                       */
N  SSP4_IRQn                   = 1,      /*!< SPI4 Interrupt                                       */
N  USB_IRQn                    = 2,      /*!< USB Host Interrupt                                   */
N  DSP_BSP1_IRQn               = 3,      /*!< DSP_BSP1 Interrupt                                   */
N  DSP_BSP2_IRQn               = 4,      /*!< DSP_BSP2 Interrupt                                   */
N  DMA_IRQn                    = 5,      /*!< DMA Interrupt                                        */
N  UART1_IRQn                  = 6,      /*!< UART1 Interrupt                                      */
N  UART2_IRQn                  = 7,      /*!< UART2 Interrupt                                      */
N  SSP1_IRQn                   = 8,      /*!< SSP1 Interrupt                                       */
N  DSP_BSP3_IRQn               = 9,      /*!< DSP_BSP3 Interrupt                                   */
N  I2C_IRQn                    = 10,     /*!< I2C Interrupt                                        */
N  Power_IRQn                  = 11,     /*!< Power Detect Interrupt                               */
N  WWDG_IRQn                   = 12,     /*!< Window Watchdog Interrupt                            */
N  DSP_DMA_IRQn				  = 13,		/*!< DSP DMA Interrupt									  */		
N  Timer1_IRQn                 = 14,     /*!< Timer1 Interrupt                                     */
N  Timer2_IRQn                 = 15,     /*!< Timer2 Interrupt                                     */
N  Timer3_IRQn                 = 16,     /*!< Timer3 Interrupt                                     */
N  ADC_IRQn                    = 17,     /*!< ADC Interrupt                                        */
N  COMPARATOR_IRQn             = 19,     /*!< COMPARATOR Interrupt                                 */
N  SSP2_IRQn                   = 20,     /*!< SSP2 Interrupt                                       */
N  DSP_ACD_IRQn                = 21,     /*!< DSP Audio Codec Interrupt                            */
N  DSP_CRPT_IRQn               = 22,     /*!< DSP Crypto Unit Interrupt                            */
N  DSP_TIM_IRQn                = 23,     /*!< DSP Timer Interrupt                                  */
N  DSP_IRQ_IRQn                = 24,     /*!< DSP Interrupts                                       */
N  DSP_STATE_IRQn              = 25,     /*!< DSP IDLE Interrupt                                   */
N  UART3_IRQn                  = 26,     /*!< UART3 Interrupt                                      */
N  BACKUP_IRQn                 = 27,     /*!< BACKUP Interrupt                                     */
N  EXT_INT1_IRQn               = 28,     /*!< EXT_INT1 Interrupt                                   */
N  EXT_INT2_IRQn               = 29,     /*!< EXT_INT2 Interrupt                                   */
N  EXT_INT3_IRQn               = 30,     /*!< EXT_INT3 Interrupt                                   */
N  EXT_INT4_IRQn               = 31      /*!< EXT_INT4 Interrupt                                   */
N}IRQn_Type;
N
N/* Includes ------------------------------------------------------------------*/
N#include "core_cm3.h"
L 1 ".\inc\core_cm3.h" 1
N/**************************************************************************//**
N * @file     core_cm3.h
N * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
N * @version  V1.30
N * @date     30. October 2009
N *
N * @note
N * Copyright (C) 2009 ARM Limited. All rights reserved.
N *
N * @par
N * ARM Limited (ARM) is supplying this software for use with Cortex-M
N * processor based microcontrollers.  This file can be freely distributed
N * within development tools that are supporting such ARM based processors.
N *
N * @par
N * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
N * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
N * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
N * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
N * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
N *
N ******************************************************************************/
N
N#ifndef __CM3_CORE_H__
N#define __CM3_CORE_H__
N
N/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration
N *
N * List of Lint messages which will be suppressed and not shown:
N *   - Error 10: \n
N *     register uint32_t __regBasePri         __asm("basepri"); \n
N *     Error 10: Expecting ';'
N * .
N *   - Error 530: \n
N *     return(__regBasePri); \n
N *     Warning 530: Symbol '__regBasePri' (line 264) not initialized
N * .
N *   - Error 550: \n
N *     __regBasePri = (basePri & 0x1ff); \n
N *     Warning 550: Symbol '__regBasePri' (line 271) not accessed
N * .
N *   - Error 754: \n
N *     uint32_t RESERVED0[24]; \n
N *     Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced
N * .
N *   - Error 750: \n
N *     #define __CM3_CORE_H__ \n
N *     Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced
N * .
N *   - Error 528: \n
N *     static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
N *     Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced
N * .
N *   - Error 751: \n
N *     } InterruptType_Type; \n
N *     Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced
N * .
N * Note:  To re-enable a Message, insert a space before 'lint' *
N *
N */
N
N/*lint -save */
N/*lint -e10  */
N/*lint -e530 */
N/*lint -e550 */
N/*lint -e754 */
N/*lint -e750 */
N/*lint -e528 */
N/*lint -e751 */
N
N
N/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions
N  This file defines all structures and symbols for CMSIS core:
N    - CMSIS version number
N    - Cortex-M core registers and bitfields
N    - Cortex-M core peripheral base address
N  @{
N */
N
N#ifdef __cplusplus
S extern "C" {
N#endif
N
N#define __CM3_CMSIS_VERSION_MAIN  (0x01)                                                       /*!< [31:16] CMSIS HAL main version */
N#define __CM3_CMSIS_VERSION_SUB   (0x30)                                                       /*!< [15:0]  CMSIS HAL sub version  */
N#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */
N
N#define __CORTEX_M                (0x03)                                                       /*!< Cortex core                    */
N
N#include <stdint.h>                           /* Include standard types */
L 1 "D:\ARM Tools\Keil MDK ARM\ARM\RV31\Inc\stdint.h" 1
N/* Copyright (C) ARM Ltd., 1999 */
N/* All rights reserved */
N
N/*
N * RCS $Revision: 137748 $
N * Checkin $Date: 2008-09-11 17:34:24 +0100 (Thu, 11 Sep 2008) $
N * Revising $Author: agrant $
N */
N
N#ifndef __stdint_h
N#define __stdint_h
N
N  #ifndef __STDINT_DECLS
N  #define __STDINT_DECLS
N
N    #undef __CLIBNS
N
N    #ifdef __cplusplus
S      namespace std {
S          #define __CLIBNS std::
S          extern "C" {
N    #else
N      #define __CLIBNS
N    #endif  /* __cplusplus */
N
N
N/*
N * 'signed' is redundant below, except for 'signed char' and if
N * the typedef is used to declare a bitfield.
N * '__int64' is used instead of 'long long' so that this header
N * can be used in --strict mode.
N */
N
N    /* 7.18.1.1 */
N
N    /* exact-width signed integer types */
Ntypedef   signed          char int8_t;
Ntypedef   signed short     int int16_t;
Ntypedef   signed           int int32_t;
Ntypedef   signed       __int64 int64_t;
N
N    /* exact-width unsigned integer types */
Ntypedef unsigned          char uint8_t;
Ntypedef unsigned short     int uint16_t;
Ntypedef unsigned           int uint32_t;
Ntypedef unsigned       __int64 uint64_t;
N
N    /* 7.18.1.2 */
N
N    /* smallest type of at least n bits */
N    /* minimum-width signed integer types */
Ntypedef   signed          char int_least8_t;
Ntypedef   signed short     int int_least16_t;
Ntypedef   signed           int int_least32_t;
Ntypedef   signed       __int64 int_least64_t;
N
N    /* minimum-width unsigned integer types */
Ntypedef unsigned          char uint_least8_t;
Ntypedef unsigned short     int uint_least16_t;
Ntypedef unsigned           int uint_least32_t;
Ntypedef unsigned       __int64 uint_least64_t;
N
N    /* 7.18.1.3 */
N
N    /* fastest minimum-width signed integer types */
Ntypedef   signed           int int_fast8_t;
Ntypedef   signed           int int_fast16_t;
Ntypedef   signed           int int_fast32_t;
Ntypedef   signed       __int64 int_fast64_t;
N
N    /* fastest minimum-width unsigned integer types */
Ntypedef unsigned           int uint_fast8_t;
Ntypedef unsigned           int uint_fast16_t;
Ntypedef unsigned           int uint_fast32_t;
Ntypedef unsigned       __int64 uint_fast64_t;
N
N    /* 7.18.1.4 integer types capable of holding object pointers */
Ntypedef   signed           int intptr_t;
Ntypedef unsigned           int uintptr_t;
N
N    /* 7.18.1.5 greatest-width integer types */
Ntypedef   signed       __int64 intmax_t;
Ntypedef unsigned       __int64 uintmax_t;
N
N
N#if !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS)
X#if !0L || 0L
N
N    /* 7.18.2.1 */
N
N    /* minimum values of exact-width signed integer types */
N#define INT8_MIN                   -128
N#define INT16_MIN                -32768
N#define INT32_MIN          (~0x7fffffff)   /* -2147483648 is unsigned */
N#define INT64_MIN  __ESCAPE__(~0x7fffffffffffffffll) /* -9223372036854775808 is unsigned */
N
N    /* maximum values of exact-width signed integer types */
N#define INT8_MAX                    127
N#define INT16_MAX                 32767
N#define INT32_MAX            2147483647
N#define INT64_MAX  __ESCAPE__(9223372036854775807ll)
N
N    /* maximum values of exact-width unsigned integer types */
N#define UINT8_MAX                   255
N#define UINT16_MAX                65535
N#define UINT32_MAX           4294967295u
N#define UINT64_MAX __ESCAPE__(18446744073709551615ull)
N
N    /* 7.18.2.2 */
N
N    /* minimum values of minimum-width signed integer types */
N#define INT_LEAST8_MIN                   -128
N#define INT_LEAST16_MIN                -32768
N#define INT_LEAST32_MIN          (~0x7fffffff)
N#define INT_LEAST64_MIN  __ESCAPE__(~0x7fffffffffffffffll)
N
N    /* maximum values of minimum-width signed integer types */
N#define INT_LEAST8_MAX                    127
N#define INT_LEAST16_MAX                 32767
N#define INT_LEAST32_MAX            2147483647
N#define INT_LEAST64_MAX  __ESCAPE__(9223372036854775807ll)
N
N    /* maximum values of minimum-width unsigned integer types */
N#define UINT_LEAST8_MAX                   255
N#define UINT_LEAST16_MAX                65535
N#define UINT_LEAST32_MAX           4294967295u
N#define UINT_LEAST64_MAX __ESCAPE__(18446744073709551615ull)
N
N    /* 7.18.2.3 */
N
N    /* minimum values of fastest minimum-width signed integer types */
N#define INT_FAST8_MIN           (~0x7fffffff)
N#define INT_FAST16_MIN          (~0x7fffffff)
N#define INT_FAST32_MIN          (~0x7fffffff)
N#define INT_FAST64_MIN  __ESCAPE__(~0x7fffffffffffffffll)
N
N    /* maximum values of fastest minimum-width signed integer types */
N#define INT_FAST8_MAX             2147483647
N#define INT_FAST16_MAX            2147483647
N#define INT_FAST32_MAX            2147483647
N#define INT_FAST64_MAX  __ESCAPE__(9223372036854775807ll)
N
N    /* maximum values of fastest minimum-width unsigned integer types */
N#define UINT_FAST8_MAX            4294967295u
N#define UINT_FAST16_MAX           4294967295u
N#define UINT_FAST32_MAX           4294967295u
N#define UINT_FAST64_MAX __ESCAPE__(18446744073709551615ull)
N
N    /* 7.18.2.4 */
N
N    /* minimum value of pointer-holding signed integer type */
N#define INTPTR_MIN (~0x7fffffff)
N
N    /* maximum value of pointer-holding signed integer type */
N#define INTPTR_MAX   2147483647
N
N    /* maximum value of pointer-holding unsigned integer type */
N#define UINTPTR_MAX  4294967295u
N
N    /* 7.18.2.5 */
N
N    /* minimum value of greatest-width signed integer type */
N#define INTMAX_MIN  __ESCAPE__(~0x7fffffffffffffffll)
N
N    /* maximum value of greatest-width signed integer type */
N#define INTMAX_MAX  __ESCAPE__(9223372036854775807ll)
N
N    /* maximum value of greatest-width unsigned integer type */
N#define UINTMAX_MAX __ESCAPE__(18446744073709551615ull)
N
N    /* 7.18.3 */
N
N    /* limits of ptrdiff_t */
N#define PTRDIFF_MIN (~0x7fffffff)
N#define PTRDIFF_MAX   2147483647
N
N    /* limits of sig_atomic_t */
N#define SIG_ATOMIC_MIN (~0x7fffffff)
N#define SIG_ATOMIC_MAX   2147483647
N
N    /* limit of size_t */
N#define SIZE_MAX 4294967295u
N
N    /* limits of wchar_t */
N    /* NB we have to undef and redef because they're defined in both
N     * stdint.h and wchar.h */
N#undef WCHAR_MIN
N#undef WCHAR_MAX
N
N#if defined(__WCHAR32)
X#if 0L
S  #define WCHAR_MIN   0
S  #define WCHAR_MAX   0xffffffffU
N#else
N  #define WCHAR_MIN   0
N  #define WCHAR_MAX   65535
N#endif
N
N    /* limits of wint_t */
N#define WINT_MIN (~0x7fffffff)
N#define WINT_MAX 2147483647
N
N#endif /* __STDC_LIMIT_MACROS */
N
N#if !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS)
X#if !0L || 0L
N
N    /* 7.18.4.1 macros for minimum-width integer constants */
N#define INT8_C(x)   (x)
N#define INT16_C(x)  (x)
N#define INT32_C(x)  (x)
N#define INT64_C(x)  __ESCAPE__(x ## ll)
N
N#define UINT8_C(x)  (x ## u)
N#define UINT16_C(x) (x ## u)
N#define UINT32_C(x) (x ## u)
N#define UINT64_C(x) __ESCAPE__(x ## ull)
N
N    /* 7.18.4.2 macros for greatest-width integer constants */
N#define INTMAX_C(x)  __ESCAPE__(x ## ll)
N#define UINTMAX_C(x) __ESCAPE__(x ## ull)
N
N#endif /* __STDC_CONSTANT_MACROS */
N
N    #ifdef __cplusplus
S         }  /* extern "C" */
S      }  /* namespace std */
N    #endif /* __cplusplus */
N  #endif /* __STDINT_DECLS */
N
N  #ifdef __cplusplus
S    #ifndef __STDINT_NO_EXPORTS
S      using ::std::int8_t;
S      using ::std::int16_t;
S      using ::std::int32_t;
S      using ::std::int64_t;
S      using ::std::uint8_t;
S      using ::std::uint16_t;
S      using ::std::uint32_t;
S      using ::std::uint64_t;
S      using ::std::int_least8_t;
S      using ::std::int_least16_t;
S      using ::std::int_least32_t;
S      using ::std::int_least64_t;
S      using ::std::uint_least8_t;
S      using ::std::uint_least16_t;
S      using ::std::uint_least32_t;
S      using ::std::uint_least64_t;
S      using ::std::int_fast8_t;
S      using ::std::int_fast16_t;
S      using ::std::int_fast32_t;
S      using ::std::int_fast64_t;
S      using ::std::uint_fast8_t;
S      using ::std::uint_fast16_t;
S      using ::std::uint_fast32_t;
S      using ::std::uint_fast64_t;
S      using ::std::intptr_t;
S      using ::std::uintptr_t;
S      using ::std::intmax_t;
S      using ::std::uintmax_t;
S    #endif 
N  #endif /* __cplusplus */
N
N#endif /* __stdint_h */
N
N/* end of stdint.h */
N
N
L 91 ".\inc\core_cm3.h" 2
N
N#if defined (__ICCARM__)
X#if 0L
S  #include <intrinsics.h>                     /* IAR Intrinsics   */
N#endif
N
N
N#ifndef __NVIC_PRIO_BITS
N  #define __NVIC_PRIO_BITS    4               /*!< standard definition for NVIC Priority Bits */
N#endif
N
N
N
N
N/**
N * IO definitions
N *
N * define access restrictions to peripheral registers
N */
N
N#ifdef __cplusplus
S  #define     __I     volatile                /*!< defines 'read only' permissions      */
N#else
N  #define     __I     volatile const          /*!< defines 'read only' permissions      */
N#endif
N#define     __O     volatile                  /*!< defines 'write only' permissions     */
N#define     __IO    volatile                  /*!< defines 'read / write' permissions   */
N
N
N
N/*******************************************************************************
N *                 Register Abstraction
N ******************************************************************************/
N/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register
N @{
N*/
N
N
N/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC
N  memory mapped structure for Nested Vectored Interrupt Controller (NVIC)
N  @{
N */
Ntypedef struct
N{
N  __IO uint32_t ISER[8];                      /*!< Offset: 0x000  Interrupt Set Enable Register           */
X  volatile uint32_t ISER[8];                       
N       uint32_t RESERVED0[24];
N  __IO uint32_t ICER[8];                      /*!< Offset: 0x080  Interrupt Clear Enable Register         */
X  volatile uint32_t ICER[8];                       
N       uint32_t RSERVED1[24];
N  __IO uint32_t ISPR[8];                      /*!< Offset: 0x100  Interrupt Set Pending Register          */
X  volatile uint32_t ISPR[8];                       
N       uint32_t RESERVED2[24];
N  __IO uint32_t ICPR[8];                      /*!< Offset: 0x180  Interrupt Clear Pending Register        */
X  volatile uint32_t ICPR[8];                       
N       uint32_t RESERVED3[24];
N  __IO uint32_t IABR[8];                      /*!< Offset: 0x200  Interrupt Active bit Register           */
X  volatile uint32_t IABR[8];                       
N       uint32_t RESERVED4[56];
N  __IO uint8_t  IP[240];                      /*!< Offset: 0x300  Interrupt Priority Register (8Bit wide) */
X  volatile uint8_t  IP[240];                       
N       uint32_t RESERVED5[644];
N  __O  uint32_t STIR;                         /*!< Offset: 0xE00  Software Trigger Interrupt Register     */
X  volatile  uint32_t STIR;                          
N}  NVIC_Type;
N/*@}*/ /* end of group CMSIS_CM3_NVIC */
N
N
N/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB
N  memory mapped structure for System Control Block (SCB)
N  @{
N */
Ntypedef struct
N{
N  __I  uint32_t CPUID;                        /*!< Offset: 0x00  CPU ID Base Register                                  */
X  volatile const  uint32_t CPUID;                         
N  __IO uint32_t ICSR;                         /*!< Offset: 0x04  Interrupt Control State Register                      */
X  volatile uint32_t ICSR;                          
N  __IO uint32_t VTOR;                         /*!< Offset: 0x08  Vector Table Offset Register                          */
X  volatile uint32_t VTOR;                          
N  __IO uint32_t AIRCR;                        /*!< Offset: 0x0C  Application Interrupt / Reset Control Register        */
X  volatile uint32_t AIRCR;                         
N  __IO uint32_t SCR;                          /*!< Offset: 0x10  System Control Register                               */
X  volatile uint32_t SCR;                           
N  __IO uint32_t CCR;                          /*!< Offset: 0x14  Configuration Control Register                        */
X  volatile uint32_t CCR;                           
N  __IO uint8_t  SHP[12];                      /*!< Offset: 0x18  System Handlers Priority Registers (4-7, 8-11, 12-15) */
X  volatile uint8_t  SHP[12];                       
N  __IO uint32_t SHCSR;                        /*!< Offset: 0x24  System Handler Control and State Register             */
X  volatile uint32_t SHCSR;                         
N  __IO uint32_t CFSR;                         /*!< Offset: 0x28  Configurable Fault Status Register                    */
X  volatile uint32_t CFSR;                          
N  __IO uint32_t HFSR;                         /*!< Offset: 0x2C  Hard Fault Status Register                            */
X  volatile uint32_t HFSR;                          
N  __IO uint32_t DFSR;                         /*!< Offset: 0x30  Debug Fault Status Register                           */
X  volatile uint32_t DFSR;                          
N  __IO uint32_t MMFAR;                        /*!< Offset: 0x34  Mem Manage Address Register                           */
X  volatile uint32_t MMFAR;                         
N  __IO uint32_t BFAR;                         /*!< Offset: 0x38  Bus Fault Address Register                            */
X  volatile uint32_t BFAR;                          
N  __IO uint32_t AFSR;                         /*!< Offset: 0x3C  Auxiliary Fault Status Register                       */
X  volatile uint32_t AFSR;                          
N  __I  uint32_t PFR[2];                       /*!< Offset: 0x40  Processor Feature Register                            */
X  volatile const  uint32_t PFR[2];                        
N  __I  uint32_t DFR;                          /*!< Offset: 0x48  Debug Feature Register                                */
X  volatile const  uint32_t DFR;                           
N  __I  uint32_t ADR;                          /*!< Offset: 0x4C  Auxiliary Feature Register                            */
X  volatile const  uint32_t ADR;                           
N  __I  uint32_t MMFR[4];                      /*!< Offset: 0x50  Memory Model Feature Register                         */
X  volatile const  uint32_t MMFR[4];                       
N  __I  uint32_t ISAR[5];                      /*!< Offset: 0x60  ISA Feature Register                                  */
X  volatile const  uint32_t ISAR[5];                       
N} SCB_Type;
N
N/* SCB CPUID Register Definitions */
N#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
N#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFul << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
N
N#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
N#define SCB_CPUID_VARIANT_Msk              (0xFul << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
N
N#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
N#define SCB_CPUID_PARTNO_Msk               (0xFFFul << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
N
N#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
N#define SCB_CPUID_REVISION_Msk             (0xFul << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
N
N/* SCB Interrupt Control State Register Definitions */
N#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
N#define SCB_ICSR_NMIPENDSET_Msk            (1ul << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
N
N#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
N#define SCB_ICSR_PENDSVSET_Msk             (1ul << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
N
N#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
N#define SCB_ICSR_PENDSVCLR_Msk             (1ul << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
N
N#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
N#define SCB_ICSR_PENDSTSET_Msk             (1ul << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
N
N#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
N#define SCB_ICSR_PENDSTCLR_Msk             (1ul << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
N
N#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
N#define SCB_ICSR_ISRPREEMPT_Msk            (1ul << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
N
N#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
N#define SCB_ICSR_ISRPENDING_Msk            (1ul << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
N
N#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
N#define SCB_ICSR_VECTPENDING_Msk           (0x1FFul << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
N
N#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
N#define SCB_ICSR_RETTOBASE_Msk             (1ul << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
N
N#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
N#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFul << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
N
N/* SCB Interrupt Control State Register Definitions */
N#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
N#define SCB_VTOR_TBLBASE_Msk               (0x1FFul << SCB_VTOR_TBLBASE_Pos)              /*!< SCB VTOR: TBLBASE Mask */
N
N#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
N#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
N
N/* SCB Application Interrupt and Reset Control Register Definitions */
N#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
N#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFul << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
N
N#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
N#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
N
N#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
N#define SCB_AIRCR_ENDIANESS_Msk            (1ul << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
N
N#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
N#define SCB_AIRCR_PRIGROUP_Msk             (7ul << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
N
N#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
N#define SCB_AIRCR_SYSRESETREQ_Msk          (1ul << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
N
N#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
N#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
N
N#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
N#define SCB_AIRCR_VECTRESET_Msk            (1ul << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
N
N/* SCB System Control Register Definitions */
N#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
N#define SCB_SCR_SEVONPEND_Msk              (1ul << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
N
N#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
N#define SCB_SCR_SLEEPDEEP_Msk              (1ul << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
N
N#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
N#define SCB_SCR_SLEEPONEXIT_Msk            (1ul << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
N
N/* SCB Configuration Control Register Definitions */
N#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
N#define SCB_CCR_STKALIGN_Msk               (1ul << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
N
N#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
N#define SCB_CCR_BFHFNMIGN_Msk              (1ul << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
N
N#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
N#define SCB_CCR_DIV_0_TRP_Msk              (1ul << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
N
N#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
N#define SCB_CCR_UNALIGN_TRP_Msk            (1ul << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
N
N#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
N#define SCB_CCR_USERSETMPEND_Msk           (1ul << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
N
N#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
N#define SCB_CCR_NONBASETHRDENA_Msk         (1ul << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
N
N/* SCB System Handler Control and State Register Definitions */
N#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
N#define SCB_SHCSR_USGFAULTENA_Msk          (1ul << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
N
N#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
N#define SCB_SHCSR_BUSFAULTENA_Msk          (1ul << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
N
N#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
N#define SCB_SHCSR_MEMFAULTENA_Msk          (1ul << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
N
N#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
N#define SCB_SHCSR_SVCALLPENDED_Msk         (1ul << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
N
N#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
N#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
N
N#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
N#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
N
N#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
N#define SCB_SHCSR_USGFAULTPENDED_Msk       (1ul << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
N
N#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
N#define SCB_SHCSR_SYSTICKACT_Msk           (1ul << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
N
N#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
N#define SCB_SHCSR_PENDSVACT_Msk            (1ul << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
N
N#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
N#define SCB_SHCSR_MONITORACT_Msk           (1ul << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
N
N#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
N#define SCB_SHCSR_SVCALLACT_Msk            (1ul << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
N
N#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
N#define SCB_SHCSR_USGFAULTACT_Msk          (1ul << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
N
N#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
N#define SCB_SHCSR_BUSFAULTACT_Msk          (1ul << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
N
N#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
N#define SCB_SHCSR_MEMFAULTACT_Msk          (1ul << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
N
N/* SCB Configurable Fault Status Registers Definitions */
N#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
N#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
N
N#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
N#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFul << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
N
N#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
N#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFul << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
N
N/* SCB Hard Fault Status Registers Definitions */
N#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
N#define SCB_HFSR_DEBUGEVT_Msk              (1ul << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
N
N#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
N#define SCB_HFSR_FORCED_Msk                (1ul << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
N
N#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
N#define SCB_HFSR_VECTTBL_Msk               (1ul << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
N
N/* SCB Debug Fault Status Register Definitions */
N#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
N#define SCB_DFSR_EXTERNAL_Msk              (1ul << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
N
N#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
N#define SCB_DFSR_VCATCH_Msk                (1ul << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
N
N#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
N#define SCB_DFSR_DWTTRAP_Msk               (1ul << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
N
N#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
N#define SCB_DFSR_BKPT_Msk                  (1ul << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
N
N#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
N#define SCB_DFSR_HALTED_Msk                (1ul << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
N/*@}*/ /* end of group CMSIS_CM3_SCB */
N
N
N/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick
N  memory mapped structure for SysTick
N  @{
N */
Ntypedef struct
N{
N  __IO uint32_t CTRL;                         /*!< Offset: 0x00  SysTick Control and Status Register */
X  volatile uint32_t CTRL;                          
N  __IO uint32_t LOAD;                         /*!< Offset: 0x04  SysTick Reload Value Register       */
X  volatile uint32_t LOAD;                          
N  __IO uint32_t VAL;                          /*!< Offset: 0x08  SysTick Current Value Register      */
X  volatile uint32_t VAL;                           
N  __I  uint32_t CALIB;                        /*!< Offset: 0x0C  SysTick Calibration Register        */
X  volatile const  uint32_t CALIB;                         
N} SysTick_Type;
N
N/* SysTick Control / Status Register Definitions */
N#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
N#define SysTick_CTRL_COUNTFLAG_Msk         (1ul << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
N
N#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
N#define SysTick_CTRL_CLKSOURCE_Msk         (1ul << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
N
N#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
N#define SysTick_CTRL_TICKINT_Msk           (1ul << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
N
N#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
N#define SysTick_CTRL_ENABLE_Msk            (1ul << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
N
N/* SysTick Reload Register Definitions */
N#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
N#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
N
N/* SysTick Current Register Definitions */
N#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
N#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFul << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
N
N/* SysTick Calibration Register Definitions */
N#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
N#define SysTick_CALIB_NOREF_Msk            (1ul << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
N
N#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
N#define SysTick_CALIB_SKEW_Msk             (1ul << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
N
N#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
N#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFul << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
N/*@}*/ /* end of group CMSIS_CM3_SysTick */
N
N
N/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM
N  memory mapped structure for Instrumentation Trace Macrocell (ITM)
N  @{
N */
Ntypedef struct
N{
N  __O  union
X  volatile  union
N  {
N    __O  uint8_t    u8;                       /*!< Offset:       ITM Stimulus Port 8-bit                   */
X    volatile  uint8_t    u8;                        
N    __O  uint16_t   u16;                      /*!< Offset:       ITM Stimulus Port 16-bit                  */
X    volatile  uint16_t   u16;                       
N    __O  uint32_t   u32;                      /*!< Offset:       ITM Stimulus Port 32-bit                  */
X    volatile  uint32_t   u32;                       
N  }  PORT [32];                               /*!< Offset: 0x00  ITM Stimulus Port Registers               */
N       uint32_t RESERVED0[864];
N  __IO uint32_t TER;                          /*!< Offset:       ITM Trace Enable Register                 */
X  volatile uint32_t TER;                           
N       uint32_t RESERVED1[15];
N  __IO uint32_t TPR;                          /*!< Offset:       ITM Trace Privilege Register              */
X  volatile uint32_t TPR;                           
N       uint32_t RESERVED2[15];
N  __IO uint32_t TCR;                          /*!< Offset:       ITM Trace Control Register                */
X  volatile uint32_t TCR;                           
N       uint32_t RESERVED3[29];
N  __IO uint32_t IWR;                          /*!< Offset:       ITM Integration Write Register            */
X  volatile uint32_t IWR;                           
N  __IO uint32_t IRR;                          /*!< Offset:       ITM Integration Read Register             */
X  volatile uint32_t IRR;                           
N  __IO uint32_t IMCR;                         /*!< Offset:       ITM Integration Mode Control Register     */
X  volatile uint32_t IMCR;                          
N       uint32_t RESERVED4[43];
N  __IO uint32_t LAR;                          /*!< Offset:       ITM Lock Access Register                  */
X  volatile uint32_t LAR;                           
N  __IO uint32_t LSR;                          /*!< Offset:       ITM Lock Status Register                  */
X  volatile uint32_t LSR;                           
N       uint32_t RESERVED5[6];
N  __I  uint32_t PID4;                         /*!< Offset:       ITM Peripheral Identification Register #4 */
X  volatile const  uint32_t PID4;                          
N  __I  uint32_t PID5;                         /*!< Offset:       ITM Peripheral Identification Register #5 */
X  volatile const  uint32_t PID5;                          
N  __I  uint32_t PID6;                         /*!< Offset:       ITM Peripheral Identification Register #6 */
X  volatile const  uint32_t PID6;                          
N  __I  uint32_t PID7;                         /*!< Offset:       ITM Peripheral Identification Register #7 */
X  volatile const  uint32_t PID7;                          
N  __I  uint32_t PID0;                         /*!< Offset:       ITM Peripheral Identification Register #0 */
X  volatile const  uint32_t PID0;                          
N  __I  uint32_t PID1;                         /*!< Offset:       ITM Peripheral Identification Register #1 */
X  volatile const  uint32_t PID1;                          
N  __I  uint32_t PID2;                         /*!< Offset:       ITM Peripheral Identification Register #2 */
X  volatile const  uint32_t PID2;                          
N  __I  uint32_t PID3;                         /*!< Offset:       ITM Peripheral Identification Register #3 */
X  volatile const  uint32_t PID3;                          
N  __I  uint32_t CID0;                         /*!< Offset:       ITM Component  Identification Register #0 */
X  volatile const  uint32_t CID0;                          
N  __I  uint32_t CID1;                         /*!< Offset:       ITM Component  Identification Register #1 */
X  volatile const  uint32_t CID1;                          
N  __I  uint32_t CID2;                         /*!< Offset:       ITM Component  Identification Register #2 */
X  volatile const  uint32_t CID2;                          
N  __I  uint32_t CID3;                         /*!< Offset:       ITM Component  Identification Register #3 */
X  volatile const  uint32_t CID3;                          
N} ITM_Type;
N
N/* ITM Trace Privilege Register Definitions */
N#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
N#define ITM_TPR_PRIVMASK_Msk               (0xFul << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
N
N/* ITM Trace Control Register Definitions */
N#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
N#define ITM_TCR_BUSY_Msk                   (1ul << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
N
N#define ITM_TCR_ATBID_Pos                  16                                             /*!< ITM TCR: ATBID Position */
N#define ITM_TCR_ATBID_Msk                  (0x7Ful << ITM_TCR_ATBID_Pos)                  /*!< ITM TCR: ATBID Mask */
N
N#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
N#define ITM_TCR_TSPrescale_Msk             (3ul << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
N
N#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
N#define ITM_TCR_SWOENA_Msk                 (1ul << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
N
N#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
N#define ITM_TCR_DWTENA_Msk                 (1ul << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
N
N#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
N#define ITM_TCR_SYNCENA_Msk                (1ul << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
N
N#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
N#define ITM_TCR_TSENA_Msk                  (1ul << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
N
N#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
N#define ITM_TCR_ITMENA_Msk                 (1ul << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
N
N/* ITM Integration Write Register Definitions */
N#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
N#define ITM_IWR_ATVALIDM_Msk               (1ul << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
N
N/* ITM Integration Read Register Definitions */
N#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
N#define ITM_IRR_ATREADYM_Msk               (1ul << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
N
N/* ITM Integration Mode Control Register Definitions */
N#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
N#define ITM_IMCR_INTEGRATION_Msk           (1ul << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
N
N/* ITM Lock Status Register Definitions */
N#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
N#define ITM_LSR_ByteAcc_Msk                (1ul << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
N
N#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
N#define ITM_LSR_Access_Msk                 (1ul << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
N
N#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
N#define ITM_LSR_Present_Msk                (1ul << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
N/*@}*/ /* end of group CMSIS_CM3_ITM */
N
N
N/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type
N  memory mapped structure for Interrupt Type
N  @{
N */
Ntypedef struct
N{
N       uint32_t RESERVED0;
N  __I  uint32_t ICTR;                         /*!< Offset: 0x04  Interrupt Control Type Register */
X  volatile const  uint32_t ICTR;                          
N#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
X#if ((0L) && (__CM3_REV >= 0x200))
S  __IO uint32_t ACTLR;                        /*!< Offset: 0x08  Auxiliary Control Register      */
N#else
N       uint32_t RESERVED1;
N#endif
N} InterruptType_Type;
N
N/* Interrupt Controller Type Register Definitions */
N#define InterruptType_ICTR_INTLINESNUM_Pos  0                                             /*!< InterruptType ICTR: INTLINESNUM Position */
N#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */
N
N/* Auxiliary Control Register Definitions */
N#define InterruptType_ACTLR_DISFOLD_Pos     2                                             /*!< InterruptType ACTLR: DISFOLD Position */
N#define InterruptType_ACTLR_DISFOLD_Msk    (1ul << InterruptType_ACTLR_DISFOLD_Pos)       /*!< InterruptType ACTLR: DISFOLD Mask */
N
N#define InterruptType_ACTLR_DISDEFWBUF_Pos  1                                             /*!< InterruptType ACTLR: DISDEFWBUF Position */
N#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos)    /*!< InterruptType ACTLR: DISDEFWBUF Mask */
N
N#define InterruptType_ACTLR_DISMCYCINT_Pos  0                                             /*!< InterruptType ACTLR: DISMCYCINT Position */
N#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos)    /*!< InterruptType ACTLR: DISMCYCINT Mask */
N/*@}*/ /* end of group CMSIS_CM3_InterruptType */
N
N
N#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
X#if 0L && (__MPU_PRESENT == 1)
S/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU
S  memory mapped structure for Memory Protection Unit (MPU)
S  @{
S */
Stypedef struct
S{
S  __I  uint32_t TYPE;                         /*!< Offset: 0x00  MPU Type Register                              */
S  __IO uint32_t CTRL;                         /*!< Offset: 0x04  MPU Control Register                           */
S  __IO uint32_t RNR;                          /*!< Offset: 0x08  MPU Region RNRber Register                     */
S  __IO uint32_t RBAR;                         /*!< Offset: 0x0C  MPU Region Base Address Register               */
S  __IO uint32_t RASR;                         /*!< Offset: 0x10  MPU Region Attribute and Size Register         */
S  __IO uint32_t RBAR_A1;                      /*!< Offset: 0x14  MPU Alias 1 Region Base Address Register       */
S  __IO uint32_t RASR_A1;                      /*!< Offset: 0x18  MPU Alias 1 Region Attribute and Size Register */
S  __IO uint32_t RBAR_A2;                      /*!< Offset: 0x1C  MPU Alias 2 Region Base Address Register       */
S  __IO uint32_t RASR_A2;                      /*!< Offset: 0x20  MPU Alias 2 Region Attribute and Size Register */
S  __IO uint32_t RBAR_A3;                      /*!< Offset: 0x24  MPU Alias 3 Region Base Address Register       */
S  __IO uint32_t RASR_A3;                      /*!< Offset: 0x28  MPU Alias 3 Region Attribute and Size Register */
S} MPU_Type;
S
S/* MPU Type Register */
S#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
S#define MPU_TYPE_IREGION_Msk               (0xFFul << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
S
S#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
S#define MPU_TYPE_DREGION_Msk               (0xFFul << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
S
S#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
S#define MPU_TYPE_SEPARATE_Msk              (1ul << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
S
S/* MPU Control Register */
S#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
S#define MPU_CTRL_PRIVDEFENA_Msk            (1ul << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
S
S#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
S#define MPU_CTRL_HFNMIENA_Msk              (1ul << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
S
S#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
S#define MPU_CTRL_ENABLE_Msk                (1ul << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
S
S/* MPU Region Number Register */
S#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
S#define MPU_RNR_REGION_Msk                 (0xFFul << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
S
S/* MPU Region Base Address Register */
S#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
S#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFul << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
S
S#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
S#define MPU_RBAR_VALID_Msk                 (1ul << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
S
S#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
S#define MPU_RBAR_REGION_Msk                (0xFul << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
S
S/* MPU Region Attribute and Size Register */
S#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: XN Position */
S#define MPU_RASR_XN_Msk                    (1ul << MPU_RASR_XN_Pos)                       /*!< MPU RASR: XN Mask */
S
S#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: AP Position */
S#define MPU_RASR_AP_Msk                    (7ul << MPU_RASR_AP_Pos)                       /*!< MPU RASR: AP Mask */
S
S#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: TEX Position */
S#define MPU_RASR_TEX_Msk                   (7ul << MPU_RASR_TEX_Pos)                      /*!< MPU RASR: TEX Mask */
S
S#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: Shareable bit Position */
S#define MPU_RASR_S_Msk                     (1ul << MPU_RASR_S_Pos)                        /*!< MPU RASR: Shareable bit Mask */
S
S#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: Cacheable bit Position */
S#define MPU_RASR_C_Msk                     (1ul << MPU_RASR_C_Pos)                        /*!< MPU RASR: Cacheable bit Mask */
S
S#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: Bufferable bit Position */
S#define MPU_RASR_B_Msk                     (1ul << MPU_RASR_B_Pos)                        /*!< MPU RASR: Bufferable bit Mask */
S
S#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
S#define MPU_RASR_SRD_Msk                   (0xFFul << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
S
S#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
S#define MPU_RASR_SIZE_Msk                  (0x1Ful << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
S
S#define MPU_RASR_ENA_Pos                     0                                            /*!< MPU RASR: Region enable bit Position */
S#define MPU_RASR_ENA_Msk                    (0x1Ful << MPU_RASR_ENA_Pos)                  /*!< MPU RASR: Region enable bit Disable Mask */
S
S/*@}*/ /* end of group CMSIS_CM3_MPU */
N#endif
N
N
N/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug
N  memory mapped structure for Core Debug Register
N  @{
N */
Ntypedef struct
N{
N  __IO uint32_t DHCSR;                        /*!< Offset: 0x00  Debug Halting Control and Status Register    */
X  volatile uint32_t DHCSR;                         
N  __O  uint32_t DCRSR;                        /*!< Offset: 0x04  Debug Core Register Selector Register        */
X  volatile  uint32_t DCRSR;                         
N  __IO uint32_t DCRDR;                        /*!< Offset: 0x08  Debug Core Register Data Register            */
X  volatile uint32_t DCRDR;                         
N  __IO uint32_t DEMCR;                        /*!< Offset: 0x0C  Debug Exception and Monitor Control Register */
X  volatile uint32_t DEMCR;                         
N} CoreDebug_Type;
N
N/* Debug Halting Control and Status Register */
N#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
N#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
N
N#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
N#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
N
N#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
N#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
N
N#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
N#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
N
N#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
N#define CoreDebug_DHCSR_S_SLEEP_Msk        (1ul << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
N
N#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
N#define CoreDebug_DHCSR_S_HALT_Msk         (1ul << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
N
N#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
N#define CoreDebug_DHCSR_S_REGRDY_Msk       (1ul << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
N
N#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
N#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
N
N#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
N#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
N
N#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
N#define CoreDebug_DHCSR_C_STEP_Msk         (1ul << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
N
N#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
N#define CoreDebug_DHCSR_C_HALT_Msk         (1ul << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
N
N#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
N#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
N
N/* Debug Core Register Selector Register */
N#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
N#define CoreDebug_DCRSR_REGWnR_Msk         (1ul << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
N
N#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
N#define CoreDebug_DCRSR_REGSEL_Msk         (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
N
N/* Debug Exception and Monitor Control Register */
N#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
N#define CoreDebug_DEMCR_TRCENA_Msk         (1ul << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
N
N#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
N#define CoreDebug_DEMCR_MON_REQ_Msk        (1ul << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
N
N#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
N#define CoreDebug_DEMCR_MON_STEP_Msk       (1ul << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
N
N#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
N#define CoreDebug_DEMCR_MON_PEND_Msk       (1ul << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
N
N#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
N#define CoreDebug_DEMCR_MON_EN_Msk         (1ul << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
N
N#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
N#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
N
N#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
N#define CoreDebug_DEMCR_VC_INTERR_Msk      (1ul << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
N
N#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
N#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
N
N#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
N#define CoreDebug_DEMCR_VC_STATERR_Msk     (1ul << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
N
N#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
N#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
N
N#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
N#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
N
N#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
N#define CoreDebug_DEMCR_VC_MMERR_Msk       (1ul << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
N
N#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
N#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
N/*@}*/ /* end of group CMSIS_CM3_CoreDebug */
N
N
N/* Memory mapping of Cortex-M3 Hardware */
N#define SCS_BASE            (0xE000E000)                              /*!< System Control Space Base Address */
N#define ITM_BASE            (0xE0000000)                              /*!< ITM Base Address                  */
N#define CoreDebug_BASE      (0xE000EDF0)                              /*!< Core Debug Base Address           */
N#define SysTick_BASE        (SCS_BASE +  0x0010)                      /*!< SysTick Base Address              */
N#define NVIC_BASE           (SCS_BASE +  0x0100)                      /*!< NVIC Base Address                 */
N#define SCB_BASE            (SCS_BASE +  0x0D00)                      /*!< System Control Block Base Address */
N
N#define InterruptType       ((InterruptType_Type *) SCS_BASE)         /*!< Interrupt Type Register           */
N#define SCB                 ((SCB_Type *)           SCB_BASE)         /*!< SCB configuration struct          */
N#define SysTick             ((SysTick_Type *)       SysTick_BASE)     /*!< SysTick configuration struct      */
N#define NVIC                ((NVIC_Type *)          NVIC_BASE)        /*!< NVIC configuration struct         */
N#define ITM                 ((ITM_Type *)           ITM_BASE)         /*!< ITM configuration struct          */
N#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct   */
N
N#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
X#if 0L && (__MPU_PRESENT == 1)
S  #define MPU_BASE          (SCS_BASE +  0x0D90)                      /*!< Memory Protection Unit            */
S  #define MPU               ((MPU_Type*)            MPU_BASE)         /*!< Memory Protection Unit            */
N#endif
N
N/*@}*/ /* end of group CMSIS_CM3_core_register */
N
N
N/*******************************************************************************
N *                Hardware Abstraction Layer
N ******************************************************************************/
N
N#if defined ( __CC_ARM   )
X#if 1L
N  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler                 */
N  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler              */
N
N#elif defined ( __ICCARM__ )
S  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler                 */
S  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
S
S#elif defined   (  __GNUC__  )
S  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler                 */
S  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler              */
S
S#elif defined   (  __TASKING__  )
S  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler             */
S  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler          */
S
S#elif defined ( __CMCARM__ )
S  #define __ASM            #pragma asm                                /*!< #pragma asm for Phyton CMC-ARM Compiler      */
S  #define __INLINE         __inline                                   /*!< inline keyword for Phyton CMC-ARM Compiler */
S
N#endif
N
N
N/* ###################  Compiler specific Intrinsics  ########################### */
N
N#if defined ( __CC_ARM   ) /*------------------RealView Compiler -----------------*/
X#if 1L  
N/* ARM armcc specific functions */
N
N#define __enable_fault_irq                __enable_fiq
N#define __disable_fault_irq               __disable_fiq
N
N#define __NOP                             __nop
N#define __WFI                             __wfi
N#define __WFE                             __wfe
N#define __SEV                             __sev
N#define __ISB()                           __isb(0)
N#define __DSB()                           __dsb(0)
N#define __DMB()                           __dmb(0)
N#define __REV                             __rev
N#define __RBIT                            __rbit
N#define __LDREXB(ptr)                     ((unsigned char ) __ldrex(ptr))
N#define __LDREXH(ptr)                     ((unsigned short) __ldrex(ptr))
N#define __LDREXW(ptr)                     ((unsigned int  ) __ldrex(ptr))
N#define __STREXB(value, ptr)              __strex(value, ptr)
N#define __STREXH(value, ptr)              __strex(value, ptr)
N#define __STREXW(value, ptr)              __strex(value, ptr)
N
N
N/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */
N/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */
N/* intrinsic void __enable_irq();     */
N/* intrinsic void __disable_irq();    */
N
N
N/**
N * @brief  Return the Process Stack Pointer
N *
N * @return ProcessStackPointer
N *
N * Return the actual process stack pointer
N */
Nextern uint32_t __get_PSP(void);
N
N/**
N * @brief  Set the Process Stack Pointer
N *
N * @param  topOfProcStack  Process Stack Pointer
N *
N * Assign the value ProcessStackPointer to the MSP
N * (process stack pointer) Cortex processor register
N */
Nextern void __set_PSP(uint32_t topOfProcStack);
N
N/**
N * @brief  Return the Main Stack Pointer
N *
N * @return Main Stack Pointer
N *
N * Return the current value of the MSP (main stack pointer)
N * Cortex processor register
N */
Nextern uint32_t __get_MSP(void);
N
N/**
N * @brief  Set the Main Stack Pointer
N *
N * @param  topOfMainStack  Main Stack Pointer
N *
N * Assign the value mainStackPointer to the MSP
N * (main stack pointer) Cortex processor register
N */
Nextern void __set_MSP(uint32_t topOfMainStack);
N
N/**
N * @brief  Reverse byte order in unsigned short value
N *
N * @param   value  value to reverse
N * @return         reversed value
N *
N * Reverse byte order in unsigned short value
N */
Nextern uint32_t __REV16(uint16_t value);
N
N/**
N * @brief  Reverse byte order in signed short value with sign extension to integer
N *
N * @param   value  value to reverse
N * @return         reversed value
N *
N * Reverse byte order in signed short value with sign extension to integer
N */
Nextern int32_t __REVSH(int16_t value);
N
N
N#if (__ARMCC_VERSION < 400000)
X#if (410894 < 400000)
S
S/**
S * @brief  Remove the exclusive lock created by ldrex
S *
S * Removes the exclusive lock which is created by ldrex.
S */
Sextern void __CLREX(void);
S
S/**
S * @brief  Return the Base Priority value
S *
S * @return BasePriority
S *
S * Return the content of the base priority register
S */
Sextern uint32_t __get_BASEPRI(void);
S
S/**
S * @brief  Set the Base Priority value
S *
S * @param  basePri  BasePriority
S *
S * Set the base priority register
S */
Sextern void __set_BASEPRI(uint32_t basePri);
S
S/**
S * @brief  Return the Priority Mask value
S *
S * @return PriMask
S *
S * Return state of the priority mask bit from the priority mask register
S */
Sextern uint32_t __get_PRIMASK(void);
S
S/**
S * @brief  Set the Priority Mask value
S *
S * @param   priMask  PriMask
S *
S * Set the priority mask bit in the priority mask register
S */
Sextern void __set_PRIMASK(uint32_t priMask);
S
S/**
S * @brief  Return the Fault Mask value
S *
S * @return FaultMask
S *
S * Return the content of the fault mask register
S */
Sextern uint32_t __get_FAULTMASK(void);
S
S/**
S * @brief  Set the Fault Mask value
S *
S * @param  faultMask faultMask value
S *
S * Set the fault mask register
S */
Sextern void __set_FAULTMASK(uint32_t faultMask);
S
S/**
S * @brief  Return the Control Register value
S *
S * @return Control value
S *
S * Return the content of the control register
S */
Sextern uint32_t __get_CONTROL(void);
S
S/**
S * @brief  Set the Control Register value
S *
S * @param  control  Control value
S *
S * Set the control register
S */
Sextern void __set_CONTROL(uint32_t control);
S
N#else  /* (__ARMCC_VERSION >= 400000)  */
N
N/**
N * @brief  Remove the exclusive lock created by ldrex
N *
N * Removes the exclusive lock which is created by ldrex.
N */
N#define __CLREX                           __clrex
N
N/**
N * @brief  Return the Base Priority value
N *
N * @return BasePriority
N *
N * Return the content of the base priority register
N */
Nstatic __INLINE uint32_t  __get_BASEPRI(void)
Xstatic __inline uint32_t  __get_BASEPRI(void)
N{
N  register uint32_t __regBasePri         __ASM("basepri");
X  register uint32_t __regBasePri         __asm("basepri");
N  return(__regBasePri);
N}
N
N/**
N * @brief  Set the Base Priority value
N *
N * @param  basePri  BasePriority
N *
N * Set the base priority register
N */
Nstatic __INLINE void __set_BASEPRI(uint32_t basePri)
Xstatic __inline void __set_BASEPRI(uint32_t basePri)
N{
N  register uint32_t __regBasePri         __ASM("basepri");
X  register uint32_t __regBasePri         __asm("basepri");
N  __regBasePri = (basePri & 0xff);
N}
N
N/**
N * @brief  Return the Priority Mask value
N *
N * @return PriMask
N *
N * Return state of the priority mask bit from the priority mask register
N */
Nstatic __INLINE uint32_t __get_PRIMASK(void)
Xstatic __inline uint32_t __get_PRIMASK(void)
N{
N  register uint32_t __regPriMask         __ASM("primask");
X  register uint32_t __regPriMask         __asm("primask");
N  return(__regPriMask);
N}
N
N/**
N * @brief  Set the Priority Mask value
N *
N * @param  priMask  PriMask
N *
N * Set the priority mask bit in the priority mask register
N */
Nstatic __INLINE void __set_PRIMASK(uint32_t priMask)
Xstatic __inline void __set_PRIMASK(uint32_t priMask)
N{
N  register uint32_t __regPriMask         __ASM("primask");
X  register uint32_t __regPriMask         __asm("primask");
N  __regPriMask = (priMask);
N}
N
N/**
N * @brief  Return the Fault Mask value
N *
N * @return FaultMask
N *
N * Return the content of the fault mask register
N */
Nstatic __INLINE uint32_t __get_FAULTMASK(void)
Xstatic __inline uint32_t __get_FAULTMASK(void)
N{
N  register uint32_t __regFaultMask       __ASM("faultmask");
X  register uint32_t __regFaultMask       __asm("faultmask");
N  return(__regFaultMask);
N}
N
N/**
N * @brief  Set the Fault Mask value
N *
N * @param  faultMask  faultMask value
N *
N * Set the fault mask register
N */
Nstatic __INLINE void __set_FAULTMASK(uint32_t faultMask)
Xstatic __inline void __set_FAULTMASK(uint32_t faultMask)
N{
N  register uint32_t __regFaultMask       __ASM("faultmask");
X  register uint32_t __regFaultMask       __asm("faultmask");
N  __regFaultMask = (faultMask & 1);
N}
N
N/**
N * @brief  Return the Control Register value
N *
N * @return Control value
N *
N * Return the content of the control register
N */
Nstatic __INLINE uint32_t __get_CONTROL(void)
Xstatic __inline uint32_t __get_CONTROL(void)
N{
N  register uint32_t __regControl         __ASM("control");
X  register uint32_t __regControl         __asm("control");
N  return(__regControl);
N}
N
N/**
N * @brief  Set the Control Register value
N *
N * @param  control  Control value
N *
N * Set the control register
N */
Nstatic __INLINE void __set_CONTROL(uint32_t control)
Xstatic __inline void __set_CONTROL(uint32_t control)
N{
N  register uint32_t __regControl         __ASM("control");
X  register uint32_t __regControl         __asm("control");
N  __regControl = control;
N}
N
N#endif /* __ARMCC_VERSION  */
N
N
N
N#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
S/* IAR iccarm specific functions */
S
S#define __enable_irq                              __enable_interrupt        /*!< global Interrupt enable */
S#define __disable_irq                             __disable_interrupt       /*!< global Interrupt disable */
S
Sstatic __INLINE void __enable_fault_irq()         { __ASM ("cpsie f"); }
Sstatic __INLINE void __disable_fault_irq()        { __ASM ("cpsid f"); }
S
S#define __NOP                                     __no_operation            /*!< no operation intrinsic in IAR Compiler */
Sstatic __INLINE  void __WFI()                     { __ASM ("wfi"); }
Sstatic __INLINE  void __WFE()                     { __ASM ("wfe"); }
Sstatic __INLINE  void __SEV()                     { __ASM ("sev"); }
Sstatic __INLINE  void __CLREX()                   { __ASM ("clrex"); }
S
S/* intrinsic void __ISB(void)                                     */
S/* intrinsic void __DSB(void)                                     */
S/* intrinsic void __DMB(void)                                     */
S/* intrinsic void __set_PRIMASK();                                */
S/* intrinsic void __get_PRIMASK();                                */
S/* intrinsic void __set_FAULTMASK();                              */
S/* intrinsic void __get_FAULTMASK();                              */
S/* intrinsic uint32_t __REV(uint32_t value);                      */
S/* intrinsic uint32_t __REVSH(uint32_t value);                    */
S/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */
S/* intrinsic unsigned long __LDREX(unsigned long *);              */
S
S#if __VER__ < 6020000
S/**
S * @brief  Return the Process Stack Pointer
S *
S * @return ProcessStackPointer
S *
S * Return the actual process stack pointer
S */
Sextern uint32_t __get_PSP(void);
S
S/**
S * @brief  Set the Process Stack Pointer
S *
S * @param  topOfProcStack  Process Stack Pointer
S *
S * Assign the value ProcessStackPointer to the MSP
S * (process stack pointer) Cortex processor register
S */
Sextern void __set_PSP(uint32_t topOfProcStack);
S
S/**
S * @brief  Return the Main Stack Pointer
S *
S * @return Main Stack Pointer
S *
S * Return the current value of the MSP (main stack pointer)
S * Cortex processor register
S */
Sextern uint32_t __get_MSP(void);
S
S/**
S * @brief  Set the Main Stack Pointer
S *
S * @param  topOfMainStack  Main Stack Pointer
S *
S * Assign the value mainStackPointer to the MSP
S * (main stack pointer) Cortex processor register
S */
Sextern void __set_MSP(uint32_t topOfMainStack);
S
S/**
S * @brief  Reverse byte order in unsigned short value
S *
S * @param  value  value to reverse
S * @return        reversed value
S *
S * Reverse byte order in unsigned short value
S */
Sextern uint32_t __REV16(uint16_t value);
S
S/**
S * @brief  Reverse bit order of value
S *
S * @param  value  value to reverse
S * @return        reversed value
S *
S * Reverse bit order of value
S */
Sextern uint32_t __RBIT(uint32_t value);
S#endif
S
S/**
S * @brief  LDR Exclusive (8 bit)
S *
S * @param  *addr  address pointer
S * @return        value of (*address)
S *
S * Exclusive LDR command for 8 bit values)
S */
Sextern uint8_t __LDREXB(uint8_t *addr);
S
S/**
S * @brief  LDR Exclusive (16 bit)
S *
S * @param  *addr  address pointer
S * @return        value of (*address)
S *
S * Exclusive LDR command for 16 bit values
S */
Sextern uint16_t __LDREXH(uint16_t *addr);
S
S/**
S * @brief  LDR Exclusive (32 bit)
S *
S * @param  *addr  address pointer
S * @return        value of (*address)
S *
S * Exclusive LDR command for 32 bit values
S */
Sextern uint32_t __LDREXW(uint32_t *addr);
S
S#if __VER__ < 6020000
S/**
S * @brief  STR Exclusive (8 bit)
S *
S * @param  value  value to store
S * @param  *addr  address pointer
S * @return        successful / failed
S *
S * Exclusive STR command for 8 bit values
S */
Sextern uint32_t __STREXB(uint8_t value, uint8_t *addr);
S
S/**
S * @brief  STR Exclusive (16 bit)
S *
S * @param  value  value to store
S * @param  *addr  address pointer
S * @return        successful / failed
S *
S * Exclusive STR command for 16 bit values
S */
Sextern uint32_t __STREXH(uint16_t value, uint16_t *addr);
S#endif
S
S/**
S * @brief  STR Exclusive (32 bit)
S *
S * @param  value  value to store
S * @param  *addr  address pointer
S * @return        successful / failed
S *
S * Exclusive STR command for 32 bit values
S */
Sextern uint32_t __STREXW(uint32_t value, uint32_t *addr);
S
S
S
S#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
S/* GNU gcc specific functions */
S
Sstatic __INLINE void __enable_irq()               { __ASM volatile ("cpsie i"); }
Sstatic __INLINE void __disable_irq()              { __ASM volatile ("cpsid i"); }
S
Sstatic __INLINE void __enable_fault_irq()         { __ASM volatile ("cpsie f"); }
Sstatic __INLINE void __disable_fault_irq()        { __ASM volatile ("cpsid f"); }
S
Sstatic __INLINE void __NOP()                      { __ASM volatile ("nop"); }
Sstatic __INLINE void __WFI()                      { __ASM volatile ("wfi"); }
Sstatic __INLINE void __WFE()                      { __ASM volatile ("wfe"); }
Sstatic __INLINE void __SEV()                      { __ASM volatile ("sev"); }
Sstatic __INLINE void __ISB()                      { __ASM volatile ("isb"); }
Sstatic __INLINE void __DSB()                      { __ASM volatile ("dsb"); }
Sstatic __INLINE void __DMB()                      { __ASM volatile ("dmb"); }
Sstatic __INLINE void __CLREX()                    { __ASM volatile ("clrex"); }
S
S
S/**
S * @brief  Return the Process Stack Pointer
S *
S * @return ProcessStackPointer
S *
S * Return the actual process stack pointer
S */
Sextern uint32_t __get_PSP(void);
S
S/**
S * @brief  Set the Process Stack Pointer
S *
S * @param  topOfProcStack  Process Stack Pointer
S *
S * Assign the value ProcessStackPointer to the MSP
S * (process stack pointer) Cortex processor register
S */
Sextern void __set_PSP(uint32_t topOfProcStack);
S
S/**
S * @brief  Return the Main Stack Pointer
S *
S * @return Main Stack Pointer
S *
S * Return the current value of the MSP (main stack pointer)
S * Cortex processor register
S */
Sextern uint32_t __get_MSP(void);
S
S/**
S * @brief  Set the Main Stack Pointer
S *
S * @param  topOfMainStack  Main Stack Pointer
S *
S * Assign the value mainStackPointer to the MSP
S * (main stack pointer) Cortex processor register
S */
Sextern void __set_MSP(uint32_t topOfMainStack);
S
S/**
S * @brief  Return the Base Priority value
S *
S * @return BasePriority
S *
S * Return the content of the base priority register
S */
Sextern uint32_t __get_BASEPRI(void);
S
S/**
S * @brief  Set the Base Priority value
S *
S * @param  basePri  BasePriority
S *
S * Set the base priority register
S */
Sextern void __set_BASEPRI(uint32_t basePri);
S
S/**
S * @brief  Return the Priority Mask value
S *
S * @return PriMask
S *
S * Return state of the priority mask bit from the priority mask register
S */
Sextern uint32_t  __get_PRIMASK(void);
S
S/**
S * @brief  Set the Priority Mask value
S *
S * @param  priMask  PriMask
S *
S * Set the priority mask bit in the priority mask register
S */
Sextern void __set_PRIMASK(uint32_t priMask);
S
S/**
S * @brief  Return the Fault Mask value
S *
S * @return FaultMask
S *
S * Return the content of the fault mask register
S */
Sextern uint32_t __get_FAULTMASK(void);
S
S/**
S * @brief  Set the Fault Mask value
S *
S * @param  faultMask  faultMask value
S *
S * Set the fault mask register
S */
Sextern void __set_FAULTMASK(uint32_t faultMask);
S
S/**
S * @brief  Return the Control Register value
S*
S*  @return Control value
S *
S * Return the content of the control register
S */
Sextern uint32_t __get_CONTROL(void);
S
S/**
S * @brief  Set the Control Register value
S *
S * @param  control  Control value
S *
S * Set the control register
S */
Sextern void __set_CONTROL(uint32_t control);
S
S/**
S * @brief  Reverse byte order in integer value
S *
S * @param  value  value to reverse
S * @return        reversed value
S *
S * Reverse byte order in integer value
S */
Sextern uint32_t __REV(uint32_t value);
S
S/**
S * @brief  Reverse byte order in unsigned short value
S *
S * @param  value  value to reverse
S * @return        reversed value
S *
S * Reverse byte order in unsigned short value
S */
Sextern uint32_t __REV16(uint16_t value);
S
S/**
S * @brief  Reverse byte order in signed short value with sign extension to integer
S *
S * @param  value  value to reverse
S * @return        reversed value
S *
S * Reverse byte order in signed short value with sign extension to integer
S */
Sextern int32_t __REVSH(int16_t value);
S
S/**
S * @brief  Reverse bit order of value
S *
S * @param  value  value to reverse
S * @return        reversed value
S *
S * Reverse bit order of value
S */
Sextern uint32_t __RBIT(uint32_t value);
S
S/**
S * @brief  LDR Exclusive (8 bit)
S *
S * @param  *addr  address pointer
S * @return        value of (*address)
S *
S * Exclusive LDR command for 8 bit value
S */
Sextern uint8_t __LDREXB(uint8_t *addr);
S
S/**
S * @brief  LDR Exclusive (16 bit)
S *
S * @param  *addr  address pointer
S * @return        value of (*address)
S *
S * Exclusive LDR command for 16 bit values
S */
Sextern uint16_t __LDREXH(uint16_t *addr);
S
S/**
S * @brief  LDR Exclusive (32 bit)
S *
S * @param  *addr  address pointer
S * @return        value of (*address)
S *
S * Exclusive LDR command for 32 bit values
S */
Sextern uint32_t __LDREXW(uint32_t *addr);
S
S/**
S * @brief  STR Exclusive (8 bit)
S *
S * @param  value  value to store
S * @param  *addr  address pointer
S * @return        successful / failed
S *
S * Exclusive STR command for 8 bit values
S */
Sextern uint32_t __STREXB(uint8_t value, uint8_t *addr);
S
S/**
S * @brief  STR Exclusive (16 bit)
S *
S * @param  value  value to store
S * @param  *addr  address pointer
S * @return        successful / failed
S *
S * Exclusive STR command for 16 bit values
S */
Sextern uint32_t __STREXH(uint16_t value, uint16_t *addr);
S
S/**
S * @brief  STR Exclusive (32 bit)
S *
S * @param  value  value to store
S * @param  *addr  address pointer
S * @return        successful / failed
S *
S * Exclusive STR command for 32 bit values
S */
Sextern uint32_t __STREXW(uint32_t value, uint32_t *addr);
S
S
S#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
S/* TASKING carm specific functions */
S
S/*
S * The CMSIS functions have been implemented as intrinsics in the compiler.
S * Please use "carm -?i" to get an up to date list of all instrinsics,
S * Including the CMSIS ones.
S */
S
S
S#elif (defined (__CMCARM__)) /*----------------- Phyton CMC-ARM Compiler ---------------*/
S/* Phyton CMC-ARM specific functions */
S
S/*
S * The CMSIS functions have been implemented as intrinsics in the compiler.
S */
S
N#endif
N
N
N/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface
N  Core  Function Interface containing:
N  - Core NVIC Functions
N  - Core SysTick Functions
N  - Core Reset Functions
N*/
N/*@{*/
N
N
N/* ##########################   NVIC functions  #################################### */
N
N/**
N * @brief  Set the Priority Grouping in NVIC Interrupt Controller
N *
N * @param  PriorityGroup is priority grouping field
N *
N * Set the priority grouping field using the required unlock sequence.
N * The parameter priority_grouping is assigned to the field
N * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.
N * In case of a conflict between priority grouping and available
N * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
N */
Nstatic __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Xstatic __inline void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
N{
N  uint32_t reg_value;
N  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);                         /* only values 0..7 are used          */
N
N  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
X  reg_value  =  ((SCB_Type *) ((0xE000E000) + 0x0D00))->AIRCR;                                                    
N  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
X  reg_value &= ~((0xFFFFul << 16) | (7ul << 8));              
N  reg_value  =  (reg_value                       |
N                (0x5FA << SCB_AIRCR_VECTKEY_Pos) |
X                (0x5FA << 16) |
N                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
N  SCB->AIRCR =  reg_value;
X  ((SCB_Type *) ((0xE000E000) + 0x0D00))->AIRCR =  reg_value;
N}
N
N/**
N * @brief  Get the Priority Grouping from NVIC Interrupt Controller
N *
N * @return priority grouping field
N *
N * Get the priority grouping from NVIC Interrupt Controller.
N * priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
N */
Nstatic __INLINE uint32_t NVIC_GetPriorityGrouping(void)
Xstatic __inline uint32_t NVIC_GetPriorityGrouping(void)
N{
N  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
X  return ((((SCB_Type *) ((0xE000E000) + 0x0D00))->AIRCR & (7ul << 8)) >> 8);    
N}
N
N/**
N * @brief  Enable Interrupt in NVIC Interrupt Controller
N *
N * @param  IRQn   The positive number of the external interrupt to enable
N *
N * Enable a device specific interupt in the NVIC interrupt controller.
N * The interrupt number cannot be a negative value.
N */
Nstatic __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Xstatic __inline void NVIC_EnableIRQ(IRQn_Type IRQn)
N{
N  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
X  ((NVIC_Type *) ((0xE000E000) + 0x0100))->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));  
N}
N
N/**
N * @brief  Disable the interrupt line for external interrupt specified
N *
N * @param  IRQn   The positive number of the external interrupt to disable
N *
N * Disable a device specific interupt in the NVIC interrupt controller.
N * The interrupt number cannot be a negative value.
N */
Nstatic __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Xstatic __inline void NVIC_DisableIRQ(IRQn_Type IRQn)
N{
N  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
X  ((NVIC_Type *) ((0xE000E000) + 0x0100))->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));  
N}
N
N/**
N * @brief  Read the interrupt pending bit for a device specific interrupt source
N *
N * @param  IRQn    The number of the device specifc interrupt
N * @return         1 = interrupt pending, 0 = interrupt not pending
N *
N * Read the pending register in NVIC and return 1 if its status is pending,
N * otherwise it returns 0
N */
Nstatic __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Xstatic __inline uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
N{
N  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
X  return((uint32_t) ((((NVIC_Type *) ((0xE000E000) + 0x0100))->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));  
N}
N
N/**
N * @brief  Set the pending bit for an external interrupt
N *
N * @param  IRQn    The number of the interrupt for set pending
N *
N * Set the pending bit for the specified interrupt.
N * The interrupt number cannot be a negative value.
N */
Nstatic __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Xstatic __inline void NVIC_SetPendingIRQ(IRQn_Type IRQn)
N{
N  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
X  ((NVIC_Type *) ((0xE000E000) + 0x0100))->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));  
N}
N
N/**
N * @brief  Clear the pending bit for an external interrupt
N *
N * @param  IRQn    The number of the interrupt for clear pending
N *
N * Clear the pending bit for the specified interrupt.
N * The interrupt number cannot be a negative value.
N */
Nstatic __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Xstatic __inline void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
N{
N  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
X  ((NVIC_Type *) ((0xE000E000) + 0x0100))->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));  
N}
N
N/**
N * @brief  Read the active bit for an external interrupt
N *
N * @param  IRQn    The number of the interrupt for read active bit
N * @return         1 = interrupt active, 0 = interrupt not active
N *
N * Read the active register in NVIC and returns 1 if its status is active,
N * otherwise it returns 0.
N */
Nstatic __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
Xstatic __inline uint32_t NVIC_GetActive(IRQn_Type IRQn)
N{
N  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
X  return((uint32_t)((((NVIC_Type *) ((0xE000E000) + 0x0100))->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));  
N}
N
N/**
N * @brief  Set the priority for an interrupt
N *
N * @param  IRQn      The number of the interrupt for set priority
N * @param  priority  The priority to set
N *
N * Set the priority for the specified interrupt. The interrupt
N * number can be positive to specify an external (device specific)
N * interrupt, or negative to specify an internal (core) interrupt.
N *
N * Note: The priority cannot be set for every core interrupt.
N */
Nstatic __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Xstatic __inline void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
N{
N  if(IRQn < 0) {
N    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */
X    ((SCB_Type *) ((0xE000E000) + 0x0D00))->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - 4)) & 0xff); }  
N  else {
N    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
X    ((NVIC_Type *) ((0xE000E000) + 0x0100))->IP[(uint32_t)(IRQn)] = ((priority << (8 - 4)) & 0xff);    }         
N}
N
N/**
N * @brief  Read the priority for an interrupt
N *
N * @param  IRQn      The number of the interrupt for get priority
N * @return           The priority for the interrupt
N *
N * Read the priority for the specified interrupt. The interrupt
N * number can be positive to specify an external (device specific)
N * interrupt, or negative to specify an internal (core) interrupt.
N *
N * The returned priority value is automatically aligned to the implemented
N * priority bits of the microcontroller.
N *
N * Note: The priority cannot be set for every core interrupt.
N */
Nstatic __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Xstatic __inline uint32_t NVIC_GetPriority(IRQn_Type IRQn)
N{
N
N  if(IRQn < 0) {
N    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M3 system interrupts */
X    return((uint32_t)(((SCB_Type *) ((0xE000E000) + 0x0D00))->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - 4)));  }  
N  else {
N    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
X    return((uint32_t)(((NVIC_Type *) ((0xE000E000) + 0x0100))->IP[(uint32_t)(IRQn)]           >> (8 - 4)));  }  
N}
N
N
N/**
N * @brief  Encode the priority for an interrupt
N *
N * @param  PriorityGroup    The used priority group
N * @param  PreemptPriority  The preemptive priority value (starting from 0)
N * @param  SubPriority      The sub priority value (starting from 0)
N * @return                  The encoded priority for the interrupt
N *
N * Encode the priority for an interrupt with the given priority group,
N * preemptive priority value and sub priority value.
N * In case of a conflict between priority grouping and available
N * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
N *
N * The returned priority value can be used for NVIC_SetPriority(...) function
N */
Nstatic __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Xstatic __inline uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
N{
N  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
N  uint32_t PreemptPriorityBits;
N  uint32_t SubPriorityBits;
N
N  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
X  PreemptPriorityBits = ((7 - PriorityGroupTmp) > 4) ? 4 : 7 - PriorityGroupTmp;
N  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
X  SubPriorityBits     = ((PriorityGroupTmp + 4) < 7) ? 0 : PriorityGroupTmp - 7 + 4;
N
N  return (
N           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
N           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
N         );
N}
N
N
N/**
N * @brief  Decode the priority of an interrupt
N *
N * @param  Priority           The priority for the interrupt
N * @param  PriorityGroup      The used priority group
N * @param  pPreemptPriority   The preemptive priority value (starting from 0)
N * @param  pSubPriority       The sub priority value (starting from 0)
N *
N * Decode an interrupt priority value with the given priority group to
N * preemptive priority value and sub priority value.
N * In case of a conflict between priority grouping and available
N * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
N *
N * The priority value can be retrieved with NVIC_GetPriority(...) function
N */
Nstatic __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
Xstatic __inline void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
N{
N  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
N  uint32_t PreemptPriorityBits;
N  uint32_t SubPriorityBits;
N
N  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
X  PreemptPriorityBits = ((7 - PriorityGroupTmp) > 4) ? 4 : 7 - PriorityGroupTmp;
N  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
X  SubPriorityBits     = ((PriorityGroupTmp + 4) < 7) ? 0 : PriorityGroupTmp - 7 + 4;
N
N  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
N  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
N}
N
N
N/* ##################################    SysTick function  ############################################ */
N
N#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)
X#if (!0L) || (__Vendor_SysTickConfig == 0)
N
N/**
N * @brief  Initialize and start the SysTick counter and its interrupt.
N *
N * @param   ticks   number of ticks between two interrupts
N * @return  1 = failed, 0 = successful
N *
N * Initialise the system tick timer and its interrupt and start the
N * system tick timer / counter in free running mode to generate
N * periodical interrupts.
N */
Nstatic __INLINE uint32_t SysTick_Config(uint32_t ticks)
Xstatic __inline uint32_t SysTick_Config(uint32_t ticks)
N{
N  if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
X  if (ticks > (0xFFFFFFul << 0))  return (1);             
N
N  SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
X  ((SysTick_Type *) ((0xE000E000) + 0x0010))->LOAD  = (ticks & (0xFFFFFFul << 0)) - 1;       
N  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Cortex-M0 System Interrupts */
X  NVIC_SetPriority (SysTick_IRQn, (1<<4) - 1);   
N  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
X  ((SysTick_Type *) ((0xE000E000) + 0x0010))->VAL   = 0;                                           
N  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
X  ((SysTick_Type *) ((0xE000E000) + 0x0010))->CTRL  = (1ul << 2) |
N                   SysTick_CTRL_TICKINT_Msk   |
X                   (1ul << 1)   |
N                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
X                   (1ul << 0);                     
N  return (0);                                                  /* Function successful */
N}
N
N#endif
N
N
N/* ##################################    Reset function  ############################################ */
N
N/**
N * @brief  Initiate a system reset request.
N *
N * Initiate a system reset request to reset the MCU
N */
Nstatic __INLINE void NVIC_SystemReset(void)
Xstatic __inline void NVIC_SystemReset(void)
N{
N  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
X  ((SCB_Type *) ((0xE000E000) + 0x0D00))->AIRCR  = ((0x5FA << 16)      |
N                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
X                 (((SCB_Type *) ((0xE000E000) + 0x0D00))->AIRCR & (7ul << 8)) |
N                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
X                 (1ul << 2));                    
N  __DSB();                                                     /* Ensure completion of memory access */
X  __dsb(0);                                                      
N  while(1);                                                    /* wait until reset */
N}
N
N
N/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */
N
N
N
N/* ##################################### Debug In/Output function ########################################### */
N
N/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface
N  Core Debug Interface containing:
N  - Core Debug Receive / Transmit Functions
N  - Core Debug Defines
N  - Core Debug Variables
N*/
N/*@{*/
N
Nextern volatile int ITM_RxBuffer;                    /*!< variable to receive characters                             */
N#define             ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
N
N
N/**
N * @brief  Outputs a character via the ITM channel 0
N *
N * @param  ch   character to output
N * @return      character to output
N *
N * The function outputs a character via the ITM channel 0.
N * The function returns when no debugger is connected that has booked the output.
N * It is blocking when a debugger is connected, but the previous character send is not transmitted.
N */
Nstatic __INLINE uint32_t ITM_SendChar (uint32_t ch)
Xstatic __inline uint32_t ITM_SendChar (uint32_t ch)
N{
N  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk)  &&      /* Trace enabled */
X  if ((((CoreDebug_Type *) (0xE000EDF0))->DEMCR & (1ul << 24))  &&       
N      (ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
X      (((ITM_Type *) (0xE0000000))->TCR & (1ul << 0))                  &&       
N      (ITM->TER & (1ul << 0)        )                    )     /* ITM Port #0 enabled */
X      (((ITM_Type *) (0xE0000000))->TER & (1ul << 0)        )                    )      
N  {
N    while (ITM->PORT[0].u32 == 0);
X    while (((ITM_Type *) (0xE0000000))->PORT[0].u32 == 0);
N    ITM->PORT[0].u8 = (uint8_t) ch;
X    ((ITM_Type *) (0xE0000000))->PORT[0].u8 = (uint8_t) ch;
N  }
N  return (ch);
N}
N
N
N/**
N * @brief  Inputs a character via variable ITM_RxBuffer
N *
N * @return      received character, -1 = no character received
N *
N * The function inputs a character via variable ITM_RxBuffer.
N * The function returns when no debugger is connected that has booked the output.
N * It is blocking when a debugger is connected, but the previous character send is not transmitted.
N */
Nstatic __INLINE int ITM_ReceiveChar (void) {
Xstatic __inline int ITM_ReceiveChar (void) {
N  int ch = -1;                               /* no character available */
N
N  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
X  if (ITM_RxBuffer != 0x5AA55AA5) {
N    ch = ITM_RxBuffer;
N    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
X    ITM_RxBuffer = 0x5AA55AA5;        
N  }
N
N  return (ch);
N}
N
N
N/**
N * @brief  Check if a character via variable ITM_RxBuffer is available
N *
N * @return      1 = character available, 0 = no character available
N *
N * The function checks  variable ITM_RxBuffer whether a character is available or not.
N * The function returns '1' if a character is available and '0' if no character is available.
N */
Nstatic __INLINE int ITM_CheckChar (void) {
Xstatic __inline int ITM_CheckChar (void) {
N
N  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
X  if (ITM_RxBuffer == 0x5AA55AA5) {
N    return (0);                                 /* no character available */
N  } else {
N    return (1);                                 /*    character available */
N  }
N}
N
N
N/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */
N
N
N#ifdef __cplusplus
S}
N#endif
N
N/*@}*/ /* end of group CMSIS_CM3_core_definitions */
N
N#endif /* __CM3_CORE_H__ */
N
N/*lint -restore */
N
L 92 ".\inc\1901BC1F.h" 2
N
N#include "1901BC1F_spi_defs.h"
L 1 ".\inc\1901BC1F_spi_defs.h" 1
N/**
N  ******************************************************************************
N  * @file    1901BC1F_spi_defs.h
N  * @author  Phyton Application Team
N  * @version V1.0.0
N  * @date    14/01/2011
N  * @brief   This file contains all the Special Function Registers definitions
N  *          for the SPI peripheral unit used in the Milandr 1901BC1F
N  *          microcontrollers.
N  ******************************************************************************
N  * @copy
N  *
N  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
N  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
N  * TIME. AS A RESULT, PHYTON SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
N  * OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
N  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
N  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
N  *
N  * <h2><center>&copy; COPYRIGHT 2010 Phyton</center></h2>
N  ******************************************************************************
N  * FILE 1901BC1F_spi_defs.h
N  */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __1901BC1F_SPI_DEFS_H
N#define __1901BC1F_SPI_DEFS_H
N
N/** @addtogroup __CMSIS CMSIS
N  * @{
N  */
N
N/** @addtogroup __1901BC1F_Peripheral_Units 1901BC1F Peripheral Units
N  * @{
N  */
N
N/** @defgroup Periph_SPI SPI
N  * @{
N  */
N
N/** @defgroup Periph_SPI_Data_Structures Data Structures
N  * @{
N  */
N
N/** @defgroup Periph_SPI_TypeDef SPI_TypeDef
N  * @{
N  */
N
Ntypedef struct
N{
N  __IO uint32_t SSPx_CR0;
X  volatile uint32_t SSPx_CR0;
N  __IO uint32_t SSPx_CR1;
X  volatile uint32_t SSPx_CR1;
N  __IO uint32_t SSPx_DR;
X  volatile uint32_t SSPx_DR;
N  __IO uint32_t SSPx_SR;
X  volatile uint32_t SSPx_SR;
N  __IO uint32_t SSPx_CPSR;
X  volatile uint32_t SSPx_CPSR;
N  __IO uint32_t SSPx_IMSC;
X  volatile uint32_t SSPx_IMSC;
N  __IO uint32_t SSPx_RIS;
X  volatile uint32_t SSPx_RIS;
N  __IO uint32_t SSPx_MIS;
X  volatile uint32_t SSPx_MIS;
N  __IO uint32_t SSPx_ICR;
X  volatile uint32_t SSPx_ICR;
N  __IO uint32_t SSPx_DMACR;
X  volatile uint32_t SSPx_DMACR;
N}SPI_TypeDef;
N
N/** @} */ /* End of group Periph_SPI_TypeDef */
N
N/** @} */ /* End of group Periph_SPI_Data_Structures */
N
N/** @defgroup Periph_SPI_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_SPI_SPI_SSPX_CR0_Bits SPI_SSPX_CR0
N  * @{
N  */
N
N#define SPI_SSPx_CR0_DSS_Pos                    0
N#define SPI_SSPx_CR0_DSS_Msk                    ((uint32_t)0x0000000F)
N
N#define SPI_SSPx_CR0_FRF_Pos                    4
N#define SPI_SSPx_CR0_FRF_Msk                    ((uint32_t)0x00000030)
N
N#define SPI_SSPx_CR0_SPO_Pos                    6
N#define SPI_SSPx_CR0_SPO                        ((uint32_t)0x00000040)
N
N#define SPI_SSPx_CR0_SPH_Pos                    7
N#define SPI_SSPx_CR0_SPH                        ((uint32_t)0x00000080)
N
N#define SPI_SSPx_CR0_SCR_Pos                    8
N#define SPI_SSPx_CR0_SCR_Msk                    ((uint32_t)0x0000FF00)
N
N
N/** @} */ /* End of group Periph_SPI_SPI_SSPX_CR0_Bits */
N
N/** @} */ /* End of group Periph_SPI_Defines */
N
N/** @defgroup Periph_SPI_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_SPI_SPI_SSPX_CR1_Bits SPI_SSPX_CR1
N  * @{
N  */
N
N#define SPI_SSPx_CR1_LBM_Pos                    0
N#define SPI_SSPx_CR1_LBM                        ((uint32_t)0x00000001)
N
N#define SPI_SSPx_CR1_SSE_Pos                    1
N#define SPI_SSPx_CR1_SSE                        ((uint32_t)0x00000002)
N
N#define SPI_SSPx_CR1_MS_Pos                     2
N#define SPI_SSPx_CR1_MS                         ((uint32_t)0x00000004)
N
N#define SPI_SSPx_CR1_SOD_Pos                    3
N#define SPI_SSPx_CR1_SOD                        ((uint32_t)0x00000008)
N
N
N/** @} */ /* End of group Periph_SPI_SPI_SSPX_CR1_Bits */
N
N/** @} */ /* End of group Periph_SPI_Defines */
N
N/** @defgroup Periph_SPI_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_SPI_SPI_SSPX_SR_Bits SPI_SSPX_SR
N  * @{
N  */
N
N#define SPI_SSPx_SR_TFE_Pos                     0
N#define SPI_SSPx_SR_TFE                         ((uint32_t)0x00000001)
N
N#define SPI_SSPx_SR_TNF_Pos                     1
N#define SPI_SSPx_SR_TNF                         ((uint32_t)0x00000002)
N
N#define SPI_SSPx_SR_RNE_Pos                     2
N#define SPI_SSPx_SR_RNE                         ((uint32_t)0x00000004)
N
N#define SPI_SSPx_SR_RFF_Pos                     3
N#define SPI_SSPx_SR_RFF                         ((uint32_t)0x00000008)
N
N#define SPI_SSPx_SR_BSY_Pos                     4
N#define SPI_SSPx_SR_BSY                         ((uint32_t)0x00000010)
N
N
N/** @} */ /* End of group Periph_SPI_SPI_SSPX_SR_Bits */
N
N/** @} */ /* End of group Periph_SPI_Defines */
N
N/** @defgroup Periph_SPI_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_SPI_SPI_SSPX_IMSC_Bits SPI_SSPX_IMSC
N  * @{
N  */
N
N#define SPI_SSPx_IMSC_RORIM_Pos                 0
N#define SPI_SSPx_IMSC_RORIM                     ((uint32_t)0x00000001)
N
N#define SPI_SSPx_IMSC_RTIM_Pos                  1
N#define SPI_SSPx_IMSC_RTIM                      ((uint32_t)0x00000002)
N
N#define SPI_SSPx_IMSC_RXIM_Pos                  2
N#define SPI_SSPx_IMSC_RXIM                      ((uint32_t)0x00000004)
N
N#define SPI_SSPx_IMSC_TXIM_Pos                  3
N#define SPI_SSPx_IMSC_TXIM                      ((uint32_t)0x00000008)
N
N
N/** @} */ /* End of group Periph_SPI_SPI_SSPX_IMSC_Bits */
N
N/** @} */ /* End of group Periph_SPI_Defines */
N
N/** @defgroup Periph_SPI_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_SPI_SPI_SSPX_RIS_Bits SPI_SSPX_RIS
N  * @{
N  */
N
N#define SPI_SSPx_RIS_RORRIS_Pos                 0
N#define SPI_SSPx_RIS_RORRIS                     ((uint32_t)0x00000001)
N
N#define SPI_SSPx_RIS_RTRIS_Pos                  1
N#define SPI_SSPx_RIS_RTRIS                      ((uint32_t)0x00000002)
N
N#define SPI_SSPx_RIS_RXRIS_Pos                  2
N#define SPI_SSPx_RIS_RXRIS                      ((uint32_t)0x00000004)
N
N#define SPI_SSPx_RIS_TXRIS_Pos                  3
N#define SPI_SSPx_RIS_TXRIS                      ((uint32_t)0x00000008)
N
N
N/** @} */ /* End of group Periph_SPI_SPI_SSPX_RIS_Bits */
N
N/** @} */ /* End of group Periph_SPI_Defines */
N
N/** @defgroup Periph_SPI_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_SPI_SPI_SSPX_MIS_Bits SPI_SSPX_MIS
N  * @{
N  */
N
N#define SPI_SSPx_MIS_RORMIS_Pos                 0
N#define SPI_SSPx_MIS_RORMIS                     ((uint32_t)0x00000001)
N
N#define SPI_SSPx_MIS_RTMIS_Pos                  1
N#define SPI_SSPx_MIS_RTMIS                      ((uint32_t)0x00000002)
N
N#define SPI_SSPx_MIS_RXMIS_Pos                  2
N#define SPI_SSPx_MIS_RXMIS                      ((uint32_t)0x00000004)
N
N#define SPI_SSPx_MIS_TXMIS_Pos                  3
N#define SPI_SSPx_MIS_TXMIS                      ((uint32_t)0x00000008)
N
N
N/** @} */ /* End of group Periph_SPI_SPI_SSPX_MIS_Bits */
N
N/** @} */ /* End of group Periph_SPI_Defines */
N
N/** @defgroup Periph_SPI_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_SPI_SPI_SSPX_ICR_Bits SPI_SSPX_ICR
N  * @{
N  */
N
N#define SPI_SSPx_ICR_RORIC_Pos                  0
N#define SPI_SSPx_ICR_RORIC                      ((uint32_t)0x00000001)
N
N#define SPI_SSPx_ICR_RTIC_Pos                   1
N#define SPI_SSPx_ICR_RTIC                       ((uint32_t)0x00000002)
N
N
N/** @} */ /* End of group Periph_SPI_SPI_SSPX_ICR_Bits */
N
N/** @} */ /* End of group Periph_SPI_Defines */
N
N/** @defgroup Periph_SPI_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_SPI_SPI_SSPX_DMACR_Bits SPI_SSPX_DMACR
N  * @{
N  */
N
N#define SPI_SSPx_DMACR_RXDMAE_Pos               0
N#define SPI_SSPx_DMACR_RXDMAE                   ((uint32_t)0x00000001)
N
N#define SPI_SSPx_DMACR_TXDMAE_Pos               1
N#define SPI_SSPx_DMACR_TXDMAE                   ((uint32_t)0x00000002)
N
N
N/** @} */ /* End of group Periph_SPI_SPI_SSPX_DMACR_Bits */
N
N/** @} */ /* End of group Periph_SPI_Defines */
N
N/** @} */ /* End of group Periph_SPI */
N
N/** @} */ /* End of group __1901BC1F_Peripheral_Units */
N
N/** @} */ /* End of group __CMSIS */
N
N#endif /* __1901BC1F_SPI_DEFS_H */
N
N/******************* (C) COPYRIGHT 2010 Phyton *********************************
N*
N* END OF FILE 1901BC1F_spi_defs.h */
L 94 ".\inc\1901BC1F.h" 2
N#include "1901BC1F_usb_defs.h"
L 1 ".\inc\1901BC1F_usb_defs.h" 1
N/**
N  ******************************************************************************
N  * @file    1901BC1F_usb_defs.h
N  * @author  Phyton Application Team
N  * @version V1.0.0
N  * @date    14/01/2011
N  * @brief   This file contains all the Special Function Registers definitions
N  *          for the USB peripheral unit used in the Milandr 1901BC1F
N  *          microcontrollers.
N  ******************************************************************************
N  * @copy
N  *
N  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
N  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
N  * TIME. AS A RESULT, PHYTON SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
N  * OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
N  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
N  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
N  *
N  * <h2><center>&copy; COPYRIGHT 2010 Phyton</center></h2>
N  ******************************************************************************
N  * FILE 1901BC1F_usb_defs.h
N  */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __1901BC1F_USB_DEFS_H
N#define __1901BC1F_USB_DEFS_H
N
N/** @addtogroup __CMSIS CMSIS
N  * @{
N  */
N
N/** @addtogroup __1901BC1F_Peripheral_Units 1901BC1F Peripheral Units
N  * @{
N  */
N
N/** @defgroup Periph_USB USB
N  * @{
N  */
N
N/**
N  * @brief USB_SEP_TypeDef ??? structure
N  */
N
Ntypedef struct
N{
N  __IO uint32_t CTRL;
X  volatile uint32_t CTRL;
N  __IO uint32_t STS;
X  volatile uint32_t STS;
N  __IO uint32_t TS;
X  volatile uint32_t TS;
N  __IO uint32_t NTS;
X  volatile uint32_t NTS;
N}_USB_SEP_TypeDef;
N
N/**
N  * @brief USB_SEP_TypeDef0 ??? structure
N  */
N
Ntypedef struct
N{
N  __IO uint32_t RXFD;
X  volatile uint32_t RXFD;
N       uint32_t RESERVED0;
N  __IO uint32_t RXFDC_L;
X  volatile uint32_t RXFDC_L;
N  __IO uint32_t RXFDC_H;
X  volatile uint32_t RXFDC_H;
N  __IO uint32_t RXFC;
X  volatile uint32_t RXFC;
N       uint32_t RESERVED1[11];
N  __IO uint32_t TXFD;
X  volatile uint32_t TXFD;
N       uint32_t RESERVED2[3];
N  __IO uint32_t TXFDC;
X  volatile uint32_t TXFDC;
N}_USB_SEP_TypeDef0;
N
N/** @defgroup Periph_USB_Data_Structures Data Structures
N  * @{
N  */
N
N/** @defgroup Periph_USB_TypeDef USB_TypeDef
N  * @{
N  */
N
Ntypedef struct
N{
N  __IO uint32_t HTXC;
X  volatile uint32_t HTXC;
N  __IO uint32_t HTXT;
X  volatile uint32_t HTXT;
N  __IO uint32_t HTXLC;
X  volatile uint32_t HTXLC;
N  __IO uint32_t HTXSE;
X  volatile uint32_t HTXSE;
N  __IO uint32_t HTXA;
X  volatile uint32_t HTXA;
N  __IO uint32_t HTXE;
X  volatile uint32_t HTXE;
N  __IO uint32_t HFN_L;
X  volatile uint32_t HFN_L;
N  __IO uint32_t HFN_H;
X  volatile uint32_t HFN_H;
N  __IO uint32_t HIS;
X  volatile uint32_t HIS;
N  __IO uint32_t HIM;
X  volatile uint32_t HIM;
N  __IO uint32_t HRXS;
X  volatile uint32_t HRXS;
N  __IO uint32_t HRXP;
X  volatile uint32_t HRXP;
N  __IO uint32_t HRXA;
X  volatile uint32_t HRXA;
N  __IO uint32_t HRXE;
X  volatile uint32_t HRXE;
N  __IO uint32_t HRXCS;
X  volatile uint32_t HRXCS;
N  __IO uint32_t HSTM;
X  volatile uint32_t HSTM;
N       uint32_t RESERVED0[16];
N  __IO uint32_t HRXFD;
X  volatile uint32_t HRXFD;
N       uint32_t RESERVED1;
N  __IO uint32_t HRXFDC_L;
X  volatile uint32_t HRXFDC_L;
N  __IO uint32_t HRXFDC_H;
X  volatile uint32_t HRXFDC_H;
N  __IO uint32_t HRXFC;
X  volatile uint32_t HRXFC;
N       uint32_t RESERVED2[11];
N  __IO uint32_t HTXFD;
X  volatile uint32_t HTXFD;
N       uint32_t RESERVED3[3];
N  __IO uint32_t HTXFDC;
X  volatile uint32_t HTXFDC;
N       uint32_t RESERVED4[11];
N  __IO uint32_t SEP0_CTRL;
X  volatile uint32_t SEP0_CTRL;
N  __IO uint32_t SEP0_STS;
X  volatile uint32_t SEP0_STS;
N  __IO uint32_t SEP0_TS;
X  volatile uint32_t SEP0_TS;
N  __IO uint32_t SEP0_NTS;
X  volatile uint32_t SEP0_NTS;
N  __IO uint32_t SEP1_CTRL;
X  volatile uint32_t SEP1_CTRL;
N  __IO uint32_t SEP1_STS;
X  volatile uint32_t SEP1_STS;
N  __IO uint32_t SEP1_TS;
X  volatile uint32_t SEP1_TS;
N  __IO uint32_t SEP1_NTS;
X  volatile uint32_t SEP1_NTS;
N  __IO uint32_t SEP2_CTRL;
X  volatile uint32_t SEP2_CTRL;
N  __IO uint32_t SEP2_STS;
X  volatile uint32_t SEP2_STS;
N  __IO uint32_t SEP2_TS;
X  volatile uint32_t SEP2_TS;
N  __IO uint32_t SEP2_NTS;
X  volatile uint32_t SEP2_NTS;
N  __IO uint32_t SEP3_CTRL;
X  volatile uint32_t SEP3_CTRL;
N  __IO uint32_t SEP3_STS;
X  volatile uint32_t SEP3_STS;
N  __IO uint32_t SEP3_TS;
X  volatile uint32_t SEP3_TS;
N  __IO uint32_t SEP3_NTS;
X  volatile uint32_t SEP3_NTS;
N  __IO uint32_t SC;
X  volatile uint32_t SC;
N  __IO uint32_t SLS;
X  volatile uint32_t SLS;
N  __IO uint32_t SIS;
X  volatile uint32_t SIS;
N  __IO uint32_t SIM;
X  volatile uint32_t SIM;
N  __IO uint32_t SA;
X  volatile uint32_t SA;
N  __IO uint32_t SFN_L;
X  volatile uint32_t SFN_L;
N  __IO uint32_t SFN_H;
X  volatile uint32_t SFN_H;
N       uint32_t RESERVED5[9];
N  __IO uint32_t SEP0_RXFD;
X  volatile uint32_t SEP0_RXFD;
N       uint32_t RESERVED6;
N  __IO uint32_t SEP0_RXFDC_L;
X  volatile uint32_t SEP0_RXFDC_L;
N  __IO uint32_t SEP0_RXFDC_H;
X  volatile uint32_t SEP0_RXFDC_H;
N  __IO uint32_t SEP0_RXFC;
X  volatile uint32_t SEP0_RXFC;
N       uint32_t RESERVED7[11];
N  __IO uint32_t SEP0_TXFD;
X  volatile uint32_t SEP0_TXFD;
N       uint32_t RESERVED8[3];
N  __IO uint32_t SEP0_TXFDC;
X  volatile uint32_t SEP0_TXFDC;
N       uint32_t RESERVED9[11];
N  __IO uint32_t SEP1_RXFD;
X  volatile uint32_t SEP1_RXFD;
N       uint32_t RESERVED10;
N  __IO uint32_t SEP1_RXFDC_L;
X  volatile uint32_t SEP1_RXFDC_L;
N  __IO uint32_t SEP1_RXFDC_H;
X  volatile uint32_t SEP1_RXFDC_H;
N  __IO uint32_t SEP1_RXFC;
X  volatile uint32_t SEP1_RXFC;
N       uint32_t RESERVED11[11];
N  __IO uint32_t SEP1_TXFD;
X  volatile uint32_t SEP1_TXFD;
N       uint32_t RESERVED12[3];
N  __IO uint32_t SEP1_TXFDC;
X  volatile uint32_t SEP1_TXFDC;
N       uint32_t RESERVED13[11];
N  __IO uint32_t SEP2_RXFD;
X  volatile uint32_t SEP2_RXFD;
N       uint32_t RESERVED14;
N  __IO uint32_t SEP2_RXFDC_L;
X  volatile uint32_t SEP2_RXFDC_L;
N  __IO uint32_t SEP2_RXFDC_H;
X  volatile uint32_t SEP2_RXFDC_H;
N  __IO uint32_t SEP2_RXFC;
X  volatile uint32_t SEP2_RXFC;
N       uint32_t RESERVED15[11];
N  __IO uint32_t SEP2_TXFD;
X  volatile uint32_t SEP2_TXFD;
N       uint32_t RESERVED16[3];
N  __IO uint32_t SEP2_TXFDC;
X  volatile uint32_t SEP2_TXFDC;
N       uint32_t RESERVED17[11];
N  __IO uint32_t SEP3_RXFD;
X  volatile uint32_t SEP3_RXFD;
N       uint32_t RESERVED18;
N  __IO uint32_t SEP3_RXFDC_L;
X  volatile uint32_t SEP3_RXFDC_L;
N  __IO uint32_t SEP3_RXFDC_H;
X  volatile uint32_t SEP3_RXFDC_H;
N  __IO uint32_t SEP3_RXFC;
X  volatile uint32_t SEP3_RXFC;
N       uint32_t RESERVED19[11];
N  __IO uint32_t SEP3_TXFD;
X  volatile uint32_t SEP3_TXFD;
N       uint32_t RESERVED20[3];
N  __IO uint32_t SEP3_TXFDC;
X  volatile uint32_t SEP3_TXFDC;
N       uint32_t RESERVED21[11];
N  __IO uint32_t HSCR;
X  volatile uint32_t HSCR;
N  __IO uint32_t HSVR;
X  volatile uint32_t HSVR;
N}USB_TypeDef;
N
N/** @} */ /* End of group Periph_USB_TypeDef */
N
N/** @} */ /* End of group Periph_USB_Data_Structures */
N
N/** @defgroup Periph_USB_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_USB_USB_HTXC_Bits USB_HTXC
N  * @{
N  */
N
N#define USB_HTXC_TREQ_Pos                       0
N#define USB_HTXC_TREQ                           ((uint32_t)0x00000001)
N
N#define USB_HTXC_SOFS_Pos                       1
N#define USB_HTXC_SOFS                           ((uint32_t)0x00000002)
N
N#define USB_HTXC_PREEN_Pos                      2
N#define USB_HTXC_PREEN                          ((uint32_t)0x00000004)
N
N#define USB_HTXC_ISOEN_Pos                      3
N#define USB_HTXC_ISOEN                          ((uint32_t)0x00000008)
N
N
N/** @} */ /* End of group Periph_USB_USB_HTXC_Bits */
N
N/** @} */ /* End of group Periph_USB_Defines */
N
N/** @defgroup Periph_USB_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_USB_USB_HTXLC_Bits USB_HTXLC
N  * @{
N  */
N
N#define USB_HTXLC_Pos                           0
N#define USB_HTXLC_Msk                           ((uint32_t)0x00000003)
N
N#define USB_HTXLC_DC_Pos                        2
N#define USB_HTXLC_DC                            ((uint32_t)0x00000004)
N
N#define USB_HTXLC_FSPL_Pos                      3
N#define USB_HTXLC_FSPL                          ((uint32_t)0x00000008)
N
N#define USB_HTXLC_FSLR_Pos                      4
N#define USB_HTXLC_FSLR                          ((uint32_t)0x00000010)
N
N
N/** @} */ /* End of group Periph_USB_USB_HTXLC_Bits */
N
N/** @} */ /* End of group Periph_USB_Defines */
N
N/** @defgroup Periph_USB_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_USB_USB_HIS_Bits USB_HIS
N  * @{
N  */
N
N#define USB_HIS_TDONE_Pos                       0
N#define USB_HIS_TDONE                           ((uint32_t)0x00000001)
N
N#define USB_HIS_RESUME_Pos                      1
N#define USB_HIS_RESUME                          ((uint32_t)0x00000002)
N
N#define USB_HIS_CONEV_Pos                       2
N#define USB_HIS_CONEV                           ((uint32_t)0x00000004)
N
N#define USB_HIS_SOFS_Pos                        3
N#define USB_HIS_SOFS                            ((uint32_t)0x00000008)
N
N
N/** @} */ /* End of group Periph_USB_USB_HIS_Bits */
N
N/** @} */ /* End of group Periph_USB_Defines */
N
N/** @defgroup Periph_USB_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_USB_USB_HIM_Bits USB_HIM
N  * @{
N  */
N
N#define USB_HIM_TDONEIE_Pos                     0
N#define USB_HIM_TDONEIE                         ((uint32_t)0x00000001)
N
N#define USB_HIM_RESUMEIE_Pos                    1
N#define USB_HIM_RESUMEIE                        ((uint32_t)0x00000002)
N
N#define USB_HIM_CONEVIE_Pos                     2
N#define USB_HIM_CONEVIE                         ((uint32_t)0x00000004)
N
N#define USB_HIM_SOFIE_Pos                       3
N#define USB_HIM_SOFIE                           ((uint32_t)0x00000008)
N
N
N/** @} */ /* End of group Periph_USB_USB_HIM_Bits */
N
N/** @} */ /* End of group Periph_USB_Defines */
N
N/** @defgroup Periph_USB_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_USB_USB_HRXS_Bits USB_HRXS
N  * @{
N  */
N
N#define USB_HRXS_CRCERR_Pos                     0
N#define USB_HRXS_CRCERR                         ((uint32_t)0x00000001)
N
N#define USB_HRXS_BSERR_Pos                      1
N#define USB_HRXS_BSERR                          ((uint32_t)0x00000002)
N
N#define USB_HRXS_RXOF_Pos                       2
N#define USB_HRXS_RXOF                           ((uint32_t)0x00000004)
N
N#define USB_HRXS_RXTO_Pos                       3
N#define USB_HRXS_RXTO                           ((uint32_t)0x00000008)
N
N#define USB_HRXS_NAKRXED_Pos                    4
N#define USB_HRXS_NAKRXED                        ((uint32_t)0x00000010)
N
N#define USB_HRXS_STALLRXED_Pos                  5
N#define USB_HRXS_STALLRXED                      ((uint32_t)0x00000020)
N
N#define USB_HRXS_ACKRXED_Pos                    6
N#define USB_HRXS_ACKRXED                        ((uint32_t)0x00000040)
N
N#define USB_HRXS_DATASEQ_Pos                    7
N#define USB_HRXS_DATASEQ                        ((uint32_t)0x00000080)
N
N
N/** @} */ /* End of group Periph_USB_USB_HRXS_Bits */
N
N/** @} */ /* End of group Periph_USB_Defines */
N
N/** @defgroup Periph_USB_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_USB_USB_SEP_CTRL_Bits USB_SEP_CTRL
N  * @{
N  */
N
N#define USB_SEP_CTRL_EPEN_Pos                   0
N#define USB_SEP_CTRL_EPEN                       ((uint32_t)0x00000001)
N
N#define USB_SEP_CTRL_EPRDY_Pos                  1
N#define USB_SEP_CTRL_EPRDY                      ((uint32_t)0x00000002)
N
N#define USB_SEP_CTRL_EPDATASEQ_Pos              2
N#define USB_SEP_CTRL_EPDATASEQ                  ((uint32_t)0x00000004)
N
N#define USB_SEP_CTRL_EPSSTALL_Pos               3
N#define USB_SEP_CTRL_EPSSTALL                   ((uint32_t)0x00000008)
N
N#define USB_SEP_CTRL_EPISOEN_Pos                4
N#define USB_SEP_CTRL_EPISOEN                    ((uint32_t)0x00000010)
N
N
N/** @} */ /* End of group Periph_USB_USB_SEP_CTRL_Bits */
N
N/** @} */ /* End of group Periph_USB_Defines */
N
N/** @defgroup Periph_USB_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_USB_USB_SEP_STS_Bits USB_SEP_STS
N  * @{
N  */
N
N#define USB_SEP_STS_SCCRCERR_Pos                0
N#define USB_SEP_STS_SCCRCERR                    ((uint32_t)0x00000001)
N
N#define USB_SEP_STS_SCBSERR_Pos                 1
N#define USB_SEP_STS_SCBSERR                     ((uint32_t)0x00000002)
N
N#define USB_SEP_STS_SCRXOF_Pos                  2
N#define USB_SEP_STS_SCRXOF                      ((uint32_t)0x00000004)
N
N#define USB_SEP_STS_SCRXTO_Pos                  3
N#define USB_SEP_STS_SCRXTO                      ((uint32_t)0x00000008)
N
N#define USB_SEP_STS_SCNAKSENT_Pos               4
N#define USB_SEP_STS_SCNAKSENT                   ((uint32_t)0x00000010)
N
N#define USB_SEP_STS_SCSTALLSENT_Pos             5
N#define USB_SEP_STS_SCSTALLSENT                 ((uint32_t)0x00000020)
N
N#define USB_SEP_STS_SCACKRXED_Pos               6
N#define USB_SEP_STS_SCACKRXED                   ((uint32_t)0x00000040)
N
N#define USB_SEP_STS_SCDATASEQ_Pos               7
N#define USB_SEP_STS_SCDATASEQ                   ((uint32_t)0x00000080)
N
N
N/** @} */ /* End of group Periph_USB_USB_SEP_STS_Bits */
N
N/** @} */ /* End of group Periph_USB_Defines */
N
N/** @defgroup Periph_USB_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_USB_USB_SC_Bits USB_SC
N  * @{
N  */
N
N#define USB_SC_SCGEN_Pos                        0
N#define USB_SC_SCGEN                            ((uint32_t)0x00000001)
N
N#define USB_SC_SCTXLS_Pos                       1
N#define USB_SC_SCTXLS_Msk                       ((uint32_t)0x00000006)
N
N#define USB_SC_SCDC_Pos                         3
N#define USB_SC_SCDC                             ((uint32_t)0x00000008)
N
N#define USB_SC_SCFSP_Pos                        4
N#define USB_SC_SCFSP                            ((uint32_t)0x00000010)
N
N#define USB_SC_SCFSR_Pos                        5
N#define USB_SC_SCFSR                            ((uint32_t)0x00000020)
N
N
N/** @} */ /* End of group Periph_USB_USB_SC_Bits */
N
N/** @} */ /* End of group Periph_USB_Defines */
N
N/** @defgroup Periph_USB_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_USB_USB_SIS_Bits USB_SIS
N  * @{
N  */
N
N#define USB_SIS_SCTDONE_Pos                     0
N#define USB_SIS_SCTDONE                         ((uint32_t)0x00000001)
N
N#define USB_SIS_SCRESUME_Pos                    1
N#define USB_SIS_SCRESUME                        ((uint32_t)0x00000002)
N
N#define USB_SIS_SCRESETEV_Pos                   2
N#define USB_SIS_SCRESETEV                       ((uint32_t)0x00000004)
N
N#define USB_SIS_SCSOFREC_Pos                    3
N#define USB_SIS_SCSOFREC                        ((uint32_t)0x00000008)
N
N#define USB_SIS_SCNAKSENT_Pos                   4
N#define USB_SIS_SCNAKSENT                       ((uint32_t)0x00000010)
N
N
N/** @} */ /* End of group Periph_USB_USB_SIS_Bits */
N
N/** @} */ /* End of group Periph_USB_Defines */
N
N/** @defgroup Periph_USB_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_USB_USB_SIM_Bits USB_SIM
N  * @{
N  */
N
N#define USB_SIM_SCTDONEIE_Pos                   0
N#define USB_SIM_SCTDONEIE                       ((uint32_t)0x00000001)
N
N#define USB_SIM_SCRESUMEIE_Pos                  1
N#define USB_SIM_SCRESUMEIE                      ((uint32_t)0x00000002)
N
N#define USB_SIM_SCRESETEVIE_Pos                 2
N#define USB_SIM_SCRESETEVIE                     ((uint32_t)0x00000004)
N
N#define USB_SIM_SCSOFRECIE_Pos                  3
N#define USB_SIM_SCSOFRECIE                      ((uint32_t)0x00000008)
N
N#define USB_SIM_SCNAKSENTIE_Pos                 4
N#define USB_SIM_SCNAKSENTIE                     ((uint32_t)0x00000010)
N
N
N/** @} */ /* End of group Periph_USB_USB_SIM_Bits */
N
N/** @} */ /* End of group Periph_USB_Defines */
N
N/** @defgroup Periph_USB_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_USB_USB_HSCR_Bits USB_HSCR
N  * @{
N  */
N
N#define USB_HSCR_HOST_MODE_Pos                  0
N#define USB_HSCR_HOST_MODE                      ((uint32_t)0x00000001)
N
N#define USB_HSCR_RESET_CORE_Pos                 1
N#define USB_HSCR_RESET_CORE                     ((uint32_t)0x00000002)
N
N#define USB_HSCR_EN_TX_Pos                      2
N#define USB_HSCR_EN_TX                          ((uint32_t)0x00000004)
N
N#define USB_HSCR_EN_RX_Pos                      3
N#define USB_HSCR_EN_RX                          ((uint32_t)0x00000008)
N
N#define USB_HSCR_DP_PULLUP_Pos                  4
N#define USB_HSCR_DP_PULLUP                      ((uint32_t)0x00000010)
N
N#define USB_HSCR_DP_PULLDOWN_Pos                5
N#define USB_HSCR_DP_PULLDOWN                    ((uint32_t)0x00000020)
N
N#define USB_HSCR_DM_PULLUP_Pos                  6
N#define USB_HSCR_DM_PULLUP                      ((uint32_t)0x00000040)
N
N#define USB_HSCR_DM_PULLDOWN_Pos                7
N#define USB_HSCR_DM_PULLDOWN                    ((uint32_t)0x00000080)
N
N
N/** @} */ /* End of group Periph_USB_USB_HSCR_Bits */
N
N/** @} */ /* End of group Periph_USB_Defines */
N
N/** @defgroup Periph_USB_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_USB_USB_HSVR_Bits USB_HSVR
N  * @{
N  */
N
N#define USB_HSVR_VERSION_Pos                    0
N#define USB_HSVR_VERSION_Msk                    ((uint32_t)0x0000000F)
N
N#define USB_HSVR_REVISION_Pos                   4
N#define USB_HSVR_REVISION_Msk                   ((uint32_t)0x000000F0)
N
N
N/** @} */ /* End of group Periph_USB_USB_HSVR_Bits */
N
N/** @} */ /* End of group Periph_USB_Defines */
N
N/** @} */ /* End of group Periph_USB */
N
N/** @} */ /* End of group __1901BC1F_Peripheral_Units */
N
N/** @} */ /* End of group __CMSIS */
N
N#endif /* __1901BC1F_USB_DEFS_H */
N
N/******************* (C) COPYRIGHT 2010 Phyton *********************************
N*
N* END OF FILE 1901BC1F_usb_defs.h */
L 95 ".\inc\1901BC1F.h" 2
N#include "1901BC1F_eeprom_defs.h"
L 1 ".\inc\1901BC1F_eeprom_defs.h" 1
N/**
N  ******************************************************************************
N  * @file    1901BC1F_eeprom_defs.h
N  * @author  Phyton Application Team
N  * @version V1.0.0
N  * @date    14/01/2011
N  * @brief   This file contains all the Special Function Registers definitions
N  *          for the EEPROM peripheral unit used in the Milandr 1901BC1F
N  *          microcontrollers.
N  ******************************************************************************
N  * @copy
N  *
N  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
N  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
N  * TIME. AS A RESULT, PHYTON SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
N  * OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
N  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
N  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
N  *
N  * <h2><center>&copy; COPYRIGHT 2010 Phyton</center></h2>
N  ******************************************************************************
N  * FILE 1901BC1F_eeprom_defs.h
N  */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __1901BC1F_EEPROM_DEFS_H
N#define __1901BC1F_EEPROM_DEFS_H
N
N/** @addtogroup __CMSIS CMSIS
N  * @{
N  */
N
N/** @addtogroup __1901BC1F_Peripheral_Units 1901BC1F Peripheral Units
N  * @{
N  */
N
N/** @defgroup Periph_EEPROM EEPROM
N  * @{
N  */
N
N/** @defgroup Periph_EEPROM_Data_Structures Data Structures
N  * @{
N  */
N
N/** @defgroup Periph_EEPROM_TypeDef EEPROM_TypeDef
N  * @{
N  */
N
Ntypedef struct
N{
N  __IO uint32_t CMD;
X  volatile uint32_t CMD;
N  __IO uint32_t ADR;
X  volatile uint32_t ADR;
N  __IO uint32_t DI;
X  volatile uint32_t DI;
N  __IO uint32_t DO;
X  volatile uint32_t DO;
N  __IO uint32_t KEY;
X  volatile uint32_t KEY;
N  __IO uint32_t CTRL;
X  volatile uint32_t CTRL;
N}EEPROM_TypeDef;
N
N/** @} */ /* End of group Periph_EEPROM_TypeDef */
N
N/** @} */ /* End of group Periph_EEPROM_Data_Structures */
N
N/** @defgroup Periph_EEPROM_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_EEPROM_EEPROM_CMD_Bits EEPROM_CMD
N  * @{
N  */
N
N#define EEPROM_CMD_CON_Pos                      0
N#define EEPROM_CMD_CON                          ((uint32_t)0x00000001)
N
N#define EEPROM_CMD_WR_Pos                       1
N#define EEPROM_CMD_WR                           ((uint32_t)0x00000002)
N
N#define EEPROM_CMD_RD_Pos                       2
N#define EEPROM_CMD_RD                           ((uint32_t)0x00000004)
N
N#define EEPROM_CMD_Delay_Pos                    3
N#define EEPROM_CMD_Delay_Msk                    ((uint32_t)0x00000038)
N
N#define EEPROM_CMD_XE_Pos                       6
N#define EEPROM_CMD_XE                           ((uint32_t)0x00000040)
N
N#define EEPROM_CMD_YE_Pos                       7
N#define EEPROM_CMD_YE                           ((uint32_t)0x00000080)
N
N#define EEPROM_CMD_SE_Pos                       8
N#define EEPROM_CMD_SE                           ((uint32_t)0x00000100)
N
N#define EEPROM_CMD_IFREN_Pos                    9
N#define EEPROM_CMD_IFREN                        ((uint32_t)0x00000200)
N
N#define EEPROM_CMD_ERASE_Pos                    10
N#define EEPROM_CMD_ERASE                        ((uint32_t)0x00000400)
N
N#define EEPROM_CMD_MAS1_Pos                     11
N#define EEPROM_CMD_MAS1                         ((uint32_t)0x00000800)
N
N#define EEPROM_CMD_PROG_Pos                     12
N#define EEPROM_CMD_PROG                         ((uint32_t)0x00001000)
N
N#define EEPROM_CMD_NVSTR_Pos                    13
N#define EEPROM_CMD_NVSTR                        ((uint32_t)0x00002000)
N
N
N/** @} */ /* End of group Periph_EEPROM_EEPROM_CMD_Bits */
N
N/** @} */ /* End of group Periph_EEPROM_Defines */
N
N/** @defgroup Periph_EEPROM_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_EEPROM_EEPROM_CTRL_Bits EEPROM_CTRL
N  * @{
N  */
N
N#define EEPROM_CTRL_ICEN_Pos                    0
N#define EEPROM_CTRL_ICEN                        ((uint32_t)0x00000001)
N
N#define EEPROM_CTRL_DCEN_Pos                    1
N#define EEPROM_CTRL_DCEN                        ((uint32_t)0x00000002)
N
N
N/** @} */ /* End of group Periph_EEPROM_EEPROM_CTRL_Bits */
N
N/** @} */ /* End of group Periph_EEPROM_Defines */
N
N/** @} */ /* End of group Periph_EEPROM */
N
N/** @} */ /* End of group __1901BC1F_Peripheral_Units */
N
N/** @} */ /* End of group __CMSIS */
N
N#endif /* __1901BC1F_EEPROM_DEFS_H */
N
N/******************* (C) COPYRIGHT 2010 Phyton *********************************
N*
N* END OF FILE 1901BC1F_eeprom_defs.h */
L 96 ".\inc\1901BC1F.h" 2
N#include "1901BC1F_rst_clk_defs.h"
L 1 ".\inc\1901BC1F_rst_clk_defs.h" 1
N/**
N  ******************************************************************************
N  * @file    1901BC1F_rst_clk_defs.h
N  * @author  Phyton Application Team
N  * @version V1.0.0
N  * @date    14/01/2011
N  * @brief   This file contains all the Special Function Registers definitions
N  *          for the RST_CLK peripheral unit used in the Milandr 1901BC1F
N  *          microcontrollers.
N  ******************************************************************************
N  * @copy
N  *
N  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
N  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
N  * TIME. AS A RESULT, PHYTON SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
N  * OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
N  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
N  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
N  *
N  * <h2><center>&copy; COPYRIGHT 2010 Phyton</center></h2>
N  ******************************************************************************
N  * FILE 1901BC1F_rst_clk_defs.h
N  */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __1901BC1F_RST_CLK_DEFS_H
N#define __1901BC1F_RST_CLK_DEFS_H
N
N/** @addtogroup __CMSIS CMSIS
N  * @{
N  */
N
N/** @addtogroup __1901BC1F_Peripheral_Units 1901BC1F Peripheral Units
N  * @{
N  */
N
N/** @defgroup Periph_RST_CLK RST_CLK
N  * @{
N  */
N
N/** @defgroup Periph_RST_CLK_Data_Structures Data Structures
N  * @{
N  */
N
N/** @defgroup Periph_RST_CLK_TypeDef RST_CLK_TypeDef
N  * @{
N  */
N
Ntypedef struct
N{
N  __IO uint32_t CLOCK_STATUS;
X  volatile uint32_t CLOCK_STATUS;
N  __IO uint32_t PLL_CONTROL;
X  volatile uint32_t PLL_CONTROL;
N  __IO uint32_t HS_CONTROL;
X  volatile uint32_t HS_CONTROL;
N  __IO uint32_t CPU_CLOCK;
X  volatile uint32_t CPU_CLOCK;
N  __IO uint32_t USB_CLOCK;
X  volatile uint32_t USB_CLOCK;
N  __IO uint32_t ADC_MCO_CLOCK;
X  volatile uint32_t ADC_MCO_CLOCK;
N  __IO uint32_t RTC_CLOCK;
X  volatile uint32_t RTC_CLOCK;
N  __IO uint32_t PER_CLOCK;
X  volatile uint32_t PER_CLOCK;
N  __IO uint32_t CAN_CLOCK;
X  volatile uint32_t CAN_CLOCK;
N  __IO uint32_t TIM_CLOCK;
X  volatile uint32_t TIM_CLOCK;
N  __IO uint32_t UART_CLOCK;
X  volatile uint32_t UART_CLOCK;
N  __IO uint32_t SSP_CLOCK;
X  volatile uint32_t SSP_CLOCK;
N  __IO uint32_t DSP_CLOCK;
X  volatile uint32_t DSP_CLOCK;
N  __IO uint32_t SSP_CLOCK2;
X  volatile uint32_t SSP_CLOCK2;
N  __IO uint32_t DSP_CONTROL_STATUS;
X  volatile uint32_t DSP_CONTROL_STATUS;
N}RST_CLK_TypeDef;
N
N/** @} */ /* End of group Periph_RST_CLK_TypeDef */
N
N/** @} */ /* End of group Periph_RST_CLK_Data_Structures */
N
N/** @defgroup Periph_RST_CLK_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_RST_CLK_RST_CLK_CLOCK_STATUS_Bits RST_CLK_CLOCK_STATUS
N  * @{
N  */
N
N#define RST_CLK_CLOCK_STATUS_PLL_USB_RDY_Pos    0
N#define RST_CLK_CLOCK_STATUS_PLL_USB_RDY        ((uint32_t)0x00000001)
N
N#define RST_CLK_CLOCK_STATUS_PLL_CPU_RDY_Pos    1
N#define RST_CLK_CLOCK_STATUS_PLL_CPU_RDY        ((uint32_t)0x00000002)
N
N#define RST_CLK_CLOCK_STATUS_HSE_RDY_Pos        2
N#define RST_CLK_CLOCK_STATUS_HSE_RDY            ((uint32_t)0x00000004)
N
N
N/** @} */ /* End of group Periph_RST_CLK_RST_CLK_CLOCK_STATUS_Bits */
N
N/** @} */ /* End of group Periph_RST_CLK_Defines */
N
N/** @defgroup Periph_RST_CLK_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_RST_CLK_RST_CLK_PLL_CONTROL_Bits RST_CLK_PLL_CONTROL
N  * @{
N  */
N
N#define RST_CLK_PLL_CONTROL_PLL_USB_ON_Pos      0
N#define RST_CLK_PLL_CONTROL_PLL_USB_ON          ((uint32_t)0x00000001)
N
N#define RST_CLK_PLL_CONTROL_PLL_USB_RLD_Pos     1
N#define RST_CLK_PLL_CONTROL_PLL_USB_RLD         ((uint32_t)0x00000002)
N
N#define RST_CLK_PLL_CONTROL_PLL_CPU_ON_Pos      2
N#define RST_CLK_PLL_CONTROL_PLL_CPU_ON          ((uint32_t)0x00000004)
N
N#define RST_CLK_PLL_CONTROL_PLL_CPU_PLD_Pos     3
N#define RST_CLK_PLL_CONTROL_PLL_CPU_PLD         ((uint32_t)0x00000008)
N
N#define RST_CLK_PLL_CONTROL_PLL_USB_MUL_Pos     4
N#define RST_CLK_PLL_CONTROL_PLL_USB_MUL_Msk     ((uint32_t)0x000000F0)
N
N#define RST_CLK_PLL_CONTROL_PLL_CPU_MUL_Pos     8
N#define RST_CLK_PLL_CONTROL_PLL_CPU_MUL_Msk     ((uint32_t)0x00000F00)
N
N
N/** @} */ /* End of group Periph_RST_CLK_RST_CLK_PLL_CONTROL_Bits */
N
N/** @} */ /* End of group Periph_RST_CLK_Defines */
N
N/** @defgroup Periph_RST_CLK_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_RST_CLK_RST_CLK_HS_CONTROL_Bits RST_CLK_HS_CONTROL
N  * @{
N  */
N
N#define RST_CLK_HS_CONTROL_HSE_ON_Pos           0
N#define RST_CLK_HS_CONTROL_HSE_ON               ((uint32_t)0x00000001)
N
N#define RST_CLK_HS_CONTROL_HSE_BYP_Pos          1
N#define RST_CLK_HS_CONTROL_HSE_BYP              ((uint32_t)0x00000002)
N
N
N/** @} */ /* End of group Periph_RST_CLK_RST_CLK_HS_CONTROL_Bits */
N
N/** @} */ /* End of group Periph_RST_CLK_Defines */
N
N/** @defgroup Periph_RST_CLK_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_RST_CLK_RST_CLK_CPU_CLOCK_Bits RST_CLK_CPU_CLOCK
N  * @{
N  */
N
N#define RST_CLK_CPU_CLOCK_CPU_C1_SEL_Pos        0
N#define RST_CLK_CPU_CLOCK_CPU_C1_SEL_Msk        ((uint32_t)0x00000003)
N
N#define RST_CLK_CPU_CLOCK_CPU_C2_SEL_Pos        2
N#define RST_CLK_CPU_CLOCK_CPU_C2_SEL            ((uint32_t)0x00000004)
N
N#define RST_CLK_CPU_CLOCK_CPU_C3_SEL_Pos        4
N#define RST_CLK_CPU_CLOCK_CPU_C3_SEL_Msk        ((uint32_t)0x000000F0)
N
N#define RST_CLK_CPU_CLOCK_HCLK_SEL_Pos          8
N#define RST_CLK_CPU_CLOCK_HCLK_SEL_Msk          ((uint32_t)0x00000300)
N
N
N/** @} */ /* End of group Periph_RST_CLK_RST_CLK_CPU_CLOCK_Bits */
N
N/** @} */ /* End of group Periph_RST_CLK_Defines */
N
N/** @defgroup Periph_RST_CLK_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_RST_CLK_RST_CLK_USB_CLOCK_Bits RST_CLK_USB_CLOCK
N  * @{
N  */
N
N#define RST_CLK_USB_CLOCK_USB_C1_SEL_Pos        0
N#define RST_CLK_USB_CLOCK_USB_C1_SEL_Msk        ((uint32_t)0x00000003)
N
N#define RST_CLK_USB_CLOCK_USB_C2_SEL_Pos        2
N#define RST_CLK_USB_CLOCK_USB_C2_SEL            ((uint32_t)0x00000004)
N
N#define RST_CLK_USB_CLOCK_CPU_C3_SEL_Pos        4
N#define RST_CLK_USB_CLOCK_CPU_C3_SEL_Msk        ((uint32_t)0x000000F0)
N
N#define RST_CLK_USB_CLOCK_USB_CL_KEN_Pos        8
N#define RST_CLK_USB_CLOCK_USB_CL_KEN            ((uint32_t)0x00000100)
N
N
N/** @} */ /* End of group Periph_RST_CLK_RST_CLK_USB_CLOCK_Bits */
N
N/** @} */ /* End of group Periph_RST_CLK_Defines */
N
N/** @defgroup Periph_RST_CLK_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_RST_CLK_RST_CLK_ADC_MCO_CLOCK_Bits RST_CLK_ADC_MCO_CLOCK
N  * @{
N  */
N
N#define RST_CLK_ADC_MCO_CLOCK_ADC_C1_SEL_Pos    0
N#define RST_CLK_ADC_MCO_CLOCK_ADC_C1_SEL_Msk    ((uint32_t)0x00000003)
N
N#define RST_CLK_ADC_MCO_CLOCK_ADC_C2_SEL_Pos    4
N#define RST_CLK_ADC_MCO_CLOCK_ADC_C2_SEL_Msk    ((uint32_t)0x00000030)
N
N#define RST_CLK_ADC_MCO_CLOCK_ADC_C3_SEL_Pos    8
N#define RST_CLK_ADC_MCO_CLOCK_ADC_C3_SEL_Msk    ((uint32_t)0x00000F00)
N
N#define RST_CLK_ADC_MCO_CLOCK_MCO_EN_Pos        12
N#define RST_CLK_ADC_MCO_CLOCK_MCO_EN            ((uint32_t)0x00001000)
N
N#define RST_CLK_ADC_MCO_CLOCK_ADC_CLK_EN_Pos    13
N#define RST_CLK_ADC_MCO_CLOCK_ADC_CLK_EN        ((uint32_t)0x00002000)
N
N
N/** @} */ /* End of group Periph_RST_CLK_RST_CLK_ADC_MCO_CLOCK_Bits */
N
N/** @} */ /* End of group Periph_RST_CLK_Defines */
N
N/** @defgroup Periph_RST_CLK_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_RST_CLK_RST_CLK_RTC_CLOCK_Bits RST_CLK_RTC_CLOCK
N  * @{
N  */
N
N#define RST_CLK_RTC_CLOCK_HSE_SEL_Pos           0
N#define RST_CLK_RTC_CLOCK_HSE_SEL_Msk           ((uint32_t)0x0000000F)
N
N#define RST_CLK_RTC_CLOCK_HSI_SEL_Pos           4
N#define RST_CLK_RTC_CLOCK_HSI_SEL_Msk           ((uint32_t)0x000000F0)
N
N#define RST_CLK_RTC_CLOCK_HSE_RTC_EN_Pos        8
N#define RST_CLK_RTC_CLOCK_HSE_RTC_EN            ((uint32_t)0x00000100)
N
N#define RST_CLK_RTC_CLOCK_HSI_RTC_EN_Pos        9
N#define RST_CLK_RTC_CLOCK_HSI_RTC_EN            ((uint32_t)0x00000200)
N
N
N/** @} */ /* End of group Periph_RST_CLK_RST_CLK_RTC_CLOCK_Bits */
N
N/** @} */ /* End of group Periph_RST_CLK_Defines */
N
N/** @defgroup Periph_RST_CLK_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_RST_CLK_RST_CLK_CAN_CLOCK_Bits RST_CLK_CAN_CLOCK
N  * @{
N  */
N
N#define RST_CLK_CAN_CLOCK_CAN1_BRG_Pos          0
N#define RST_CLK_CAN_CLOCK_CAN1_BRG_Msk          ((uint32_t)0x000000FF)
N
N#define RST_CLK_CAN_CLOCK_CAN2_BRG_Pos          8
N#define RST_CLK_CAN_CLOCK_CAN2_BRG_Msk          ((uint32_t)0x0000FF00)
N
N#define RST_CLK_CAN_CLOCK_CAN1_CLK_EN_Pos       24
N#define RST_CLK_CAN_CLOCK_CAN1_CLK_EN           ((uint32_t)0x01000000)
N
N#define RST_CLK_CAN_CLOCK_CAN2_CLK_EN_Pos       25
N#define RST_CLK_CAN_CLOCK_CAN2_CLK_EN           ((uint32_t)0x02000000)
N
N
N/** @} */ /* End of group Periph_RST_CLK_RST_CLK_CAN_CLOCK_Bits */
N
N/** @} */ /* End of group Periph_RST_CLK_Defines */
N
N/** @defgroup Periph_RST_CLK_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_RST_CLK_RST_CLK_TIM_CLOCK_Bits RST_CLK_TIM_CLOCK
N  * @{
N  */
N
N#define RST_CLK_TIM_CLOCK_TIM1_BRG_Pos          0
N#define RST_CLK_TIM_CLOCK_TIM1_BRG_Msk          ((uint32_t)0x000000FF)
N
N#define RST_CLK_TIM_CLOCK_TIM2_BRG_Pos          8
N#define RST_CLK_TIM_CLOCK_TIM2_BRG_Msk          ((uint32_t)0x0000FF00)
N
N#define RST_CLK_TIM_CLOCK_TIM3_BRG_Pos          16
N#define RST_CLK_TIM_CLOCK_TIM3_BRG_Msk          ((uint32_t)0x00FF0000)
N
N#define RST_CLK_TIM_CLOCK_TIM1_CLK_EN_Pos       24
N#define RST_CLK_TIM_CLOCK_TIM1_CLK_EN           ((uint32_t)0x01000000)
N
N#define RST_CLK_TIM_CLOCK_TIM2_CLK_EN_Pos       25
N#define RST_CLK_TIM_CLOCK_TIM2_CLK_EN           ((uint32_t)0x02000000)
N
N#define RST_CLK_TIM_CLOCK_TIM3_CLK_EN_Pos       26
N#define RST_CLK_TIM_CLOCK_TIM3_CLK_EN           ((uint32_t)0x04000000)
N
N
N/** @} */ /* End of group Periph_RST_CLK_RST_CLK_TIM_CLOCK_Bits */
N
N/** @} */ /* End of group Periph_RST_CLK_Defines */
N
N/** @defgroup Periph_RST_CLK_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_RST_CLK_RST_CLK_UART_CLOCK_Bits RST_CLK_UART_CLOCK
N  * @{
N  */
N
N#define RST_CLK_UART_CLOCK_UART1_BRG_Pos        0
N#define RST_CLK_UART_CLOCK_UART1_BRG_Msk        ((uint32_t)0x000000FF)
N
N#define RST_CLK_UART_CLOCK_UART2_BRG_Pos        8
N#define RST_CLK_UART_CLOCK_UART2_BRG_Msk        ((uint32_t)0x0000FF00)
N
N#define RST_CLK_UART_CLOCK_UART1_CLK_EN_Pos     24
N#define RST_CLK_UART_CLOCK_UART1_CLK_EN         ((uint32_t)0x01000000)
N
N#define RST_CLK_UART_CLOCK_UART2_CLK_EN_Pos     25
N#define RST_CLK_UART_CLOCK_UART2_CLK_EN         ((uint32_t)0x02000000)
N
N
N/** @} */ /* End of group Periph_RST_CLK_RST_CLK_UART_CLOCK_Bits */
N
N/** @} */ /* End of group Periph_RST_CLK_Defines */
N
N/** @defgroup Periph_RST_CLK_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_RST_CLK_RST_CLK_SSP_CLOCK_Bits RST_CLK_SSP_CLOCK
N  * @{
N  */
N
N#define RST_CLK_SSP_CLOCK_SSP1_BRG_Pos          0
N#define RST_CLK_SSP_CLOCK_SSP1_BRG_Msk          ((uint32_t)0x000000FF)
N
N#define RST_CLK_SSP_CLOCK_SSP2_BRG_Pos          8
N#define RST_CLK_SSP_CLOCK_SSP2_BRG_Msk          ((uint32_t)0x0000FF00)
N
N#define RST_CLK_SSP_CLOCK_SSP1_CLK_EN_Pos       24
N#define RST_CLK_SSP_CLOCK_SSP1_CLK_EN           ((uint32_t)0x01000000)
N
N#define RST_CLK_SSP_CLOCK_SSP2_CLK_EN_Pos       25
N#define RST_CLK_SSP_CLOCK_SSP2_CLK_EN           ((uint32_t)0x02000000)
N
N
N/** @} */ /* End of group Periph_RST_CLK_RST_CLK_SSP_CLOCK_Bits */
N
N/** @} */ /* End of group Periph_RST_CLK_Defines */
N
N/** @defgroup Periph_RST_CLK_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_RST_CLK_RST_CLK_DSP_CLOCK_Bits RST_CLK_DSP_CLOCK
N  * @{
N  */
N
N#define RST_CLK_DSP_CLOCK_DSP_C1_SEL_Pos        0
N#define RST_CLK_DSP_CLOCK_DSP_C1_SEL_Msk        ((uint32_t)0x00000003)
N
N#define RST_CLK_DSP_CLOCK_DSP_C2_SEL_Pos        2
N#define RST_CLK_DSP_CLOCK_DSP_C2_SEL            ((uint32_t)0x00000004)
N
N#define RST_CLK_DSP_CLOCK_DSP_C3_SEL_Pos        4
N#define RST_CLK_DSP_CLOCK_DSP_C3_SEL            ((uint32_t)0x00000010)
N
N#define RST_CLK_DSP_CLOCK_DSP_CLK_EN_Pos        8
N#define RST_CLK_DSP_CLOCK_DSP_CLK_EN            ((uint32_t)0x00000100)
N
N
N/** @} */ /* End of group Periph_RST_CLK_RST_CLK_DSP_CLOCK_Bits */
N
N/** @} */ /* End of group Periph_RST_CLK_Defines */
N
N/** @defgroup Periph_RST_CLK_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_RST_CLK_RST_CLK_SSP_CLOCK2_Bits RST_CLK_SSP_CLOCK2
N  * @{
N  */
N
N#define RST_CLK_SSP_CLOCK2_SSP4_BRG_Pos         0
N#define RST_CLK_SSP_CLOCK2_SSP4_BRG_Msk         ((uint32_t)0x000000FF)
N
N#define RST_CLK_SSP_CLOCK2_SSP4_CLK_EN_Pos      24
N#define RST_CLK_SSP_CLOCK2_SSP4_CLK_EN          ((uint32_t)0x01000000)
N
N
N/** @} */ /* End of group Periph_RST_CLK_RST_CLK_SSP_CLOCK2_Bits */
N
N/** @} */ /* End of group Periph_RST_CLK_Defines */
N
N/** @defgroup Periph_RST_CLK_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_RST_CLK_RST_CLK_DSP_CONTROL_STATUS_Bits RST_CLK_DSP_CONTROL_STATUS
N  * @{
N  */
N
N#define RST_CLK_DSP_CONTROL_STATUS_RST_DSP_ALL_Pos 0
N#define RST_CLK_DSP_CONTROL_STATUS_RST_DSP_ALL  ((uint32_t)0x00000001)
N
N#define RST_CLK_DSP_CONTROL_STATUS_RST_DSP_CPU_Pos 1
N#define RST_CLK_DSP_CONTROL_STATUS_RST_DSP_CPU  ((uint32_t)0x00000002)
N
N#define RST_CLK_DSP_CONTROL_STATUS_RST_DSP_MEM_Pos 2
N#define RST_CLK_DSP_CONTROL_STATUS_RST_DSP_MEM  ((uint32_t)0x00000004)
N
N#define RST_CLK_DSP_CONTROL_STATUS_RST_DSP_PER_Pos 3
N#define RST_CLK_DSP_CONTROL_STATUS_RST_DSP_PER  ((uint32_t)0x00000008)
N
N#define RST_CLK_DSP_CONTROL_STATUS_HOLD_Pos     4
N#define RST_CLK_DSP_CONTROL_STATUS_HOLD         ((uint32_t)0x00000010)
N
N#define RST_CLK_DSP_CONTROL_STATUS_BIO_Pos      5
N#define RST_CLK_DSP_CONTROL_STATUS_BIO          ((uint32_t)0x00000020)
N
N#define RST_CLK_DSP_CONTROL_STATUS_XF_Pos       8
N#define RST_CLK_DSP_CONTROL_STATUS_XF           ((uint32_t)0x00000100)
N
N#define RST_CLK_DSP_CONTROL_STATUS_HOLDA_Pos    9
N#define RST_CLK_DSP_CONTROL_STATUS_HOLDA        ((uint32_t)0x00000200)
N
N#define RST_CLK_DSP_CONTROL_STATUS_DSP_STATE_Pos 10
N#define RST_CLK_DSP_CONTROL_STATUS_DSP_STATE_Msk ((uint32_t)0x00000C00)
N
N#define RST_CLK_DSP_CONTROL_STATUS_BRTRD_Pos    14
N#define RST_CLK_DSP_CONTROL_STATUS_BRTRD        ((uint32_t)0x00004000)
N
N#define RST_CLK_DSP_CONTROL_STATUS_RD_BUFF_EN_Pos 15
N#define RST_CLK_DSP_CONTROL_STATUS_RD_BUFF_EN   ((uint32_t)0x00008000)
N
N
N/** @} */ /* End of group Periph_RST_CLK_RST_CLK_DSP_CONTROL_STATUS_Bits */
N
N/** @} */ /* End of group Periph_RST_CLK_Defines */
N
N/** @} */ /* End of group Periph_RST_CLK */
N
N/** @} */ /* End of group __1901BC1F_Peripheral_Units */
N
N/** @} */ /* End of group __CMSIS */
N
N#endif /* __1901BC1F_RST_CLK_DEFS_H */
N
N/******************* (C) COPYRIGHT 2010 Phyton *********************************
N*
N* END OF FILE 1901BC1F_rst_clk_defs.h */
L 97 ".\inc\1901BC1F.h" 2
N#include "1901BC1F_dma_defs.h"
L 1 ".\inc\1901BC1F_dma_defs.h" 1
N/**
N  ******************************************************************************
N  * @file    1901BC1F_dma_defs.h
N  * @author  Phyton Application Team
N  * @version V1.0.0
N  * @date    14/01/2011
N  * @brief   This file contains all the Special Function Registers definitions
N  *          for the DMA peripheral unit used in the Milandr 1901BC1F
N  *          microcontrollers.
N  ******************************************************************************
N  * @copy
N  *
N  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
N  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
N  * TIME. AS A RESULT, PHYTON SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
N  * OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
N  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
N  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
N  *
N  * <h2><center>&copy; COPYRIGHT 2010 Phyton</center></h2>
N  ******************************************************************************
N  * FILE 1901BC1F_dma_defs.h
N  */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __1901BC1F_DMA_DEFS_H
N#define __1901BC1F_DMA_DEFS_H
N
N/** @addtogroup __CMSIS CMSIS
N  * @{
N  */
N
N/** @addtogroup __1901BC1F_Peripheral_Units 1901BC1F Peripheral Units
N  * @{
N  */
N
N/** @defgroup Periph_DMA DMA
N  * @{
N  */
N
N/** @defgroup Periph_DMA_Data_Structures Data Structures
N  * @{
N  */
N
N/** @defgroup Periph_DMA_TypeDef DMA_TypeDef
N  * @{
N  */
N
Ntypedef struct
N{
N  __IO uint32_t STATUS;
X  volatile uint32_t STATUS;
N  __IO uint32_t CFG;
X  volatile uint32_t CFG;
N  __IO uint32_t CTRL_BASE_PTR;
X  volatile uint32_t CTRL_BASE_PTR;
N  __IO uint32_t ALT_CTRL_BASE_PTR;
X  volatile uint32_t ALT_CTRL_BASE_PTR;
N  __IO uint32_t WAITONREQ_STATUS;
X  volatile uint32_t WAITONREQ_STATUS;
N  __IO uint32_t CHNL_SW_REQUEST;
X  volatile uint32_t CHNL_SW_REQUEST;
N  __IO uint32_t CHNL_USEBURST_SET;
X  volatile uint32_t CHNL_USEBURST_SET;
N  __IO uint32_t CHNL_USEBURST_CLR;
X  volatile uint32_t CHNL_USEBURST_CLR;
N  __IO uint32_t CHNL_REQ_MASK_SET;
X  volatile uint32_t CHNL_REQ_MASK_SET;
N  __IO uint32_t CHNL_REQ_MASK_CLR;
X  volatile uint32_t CHNL_REQ_MASK_CLR;
N  __IO uint32_t CHNL_ENABLE_SET;
X  volatile uint32_t CHNL_ENABLE_SET;
N  __IO uint32_t CHNL_ENABLE_CLR;
X  volatile uint32_t CHNL_ENABLE_CLR;
N  __IO uint32_t CHNL_PRI_ALT_SET;
X  volatile uint32_t CHNL_PRI_ALT_SET;
N  __IO uint32_t CHNL_PRI_ALT_CLR;
X  volatile uint32_t CHNL_PRI_ALT_CLR;
N  __IO uint32_t CHNL_PRIORITY_SET;
X  volatile uint32_t CHNL_PRIORITY_SET;
N  __IO uint32_t CHNL_PRIORITY_CLR;
X  volatile uint32_t CHNL_PRIORITY_CLR;
N       uint32_t RESERVED0[3];
N  __IO uint32_t ERR_CLR;
X  volatile uint32_t ERR_CLR;
N}DMA_TypeDef;
N
N/** @} */ /* End of group Periph_DMA_TypeDef */
N
N/** @} */ /* End of group Periph_DMA_Data_Structures */
N
N/** @defgroup Periph_DMA_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_DMA_DMA_STATUS_Bits DMA_STATUS
N  * @{
N  */
N
N#define DMA_STATUS_MASTER_ENABLE_Pos            0
N#define DMA_STATUS_MASTER_ENABLE                ((uint32_t)0x00000001)
N
N#define DMA_STATUS_STATE_Pos                    4
N#define DMA_STATUS_STATE_Msk                    ((uint32_t)0x000000F0)
N
N#define DMA_STATUS_CHNLS_MINUS1_Pos             16
N#define DMA_STATUS_CHNLS_MINUS1_Msk             ((uint32_t)0x001F0000)
N
N#define DMA_STATUS_TEST_STATUS_Pos              28
N#define DMA_STATUS_TEST_STATUS_Msk              ((uint32_t)0xF0000000)
N
N
N/** @} */ /* End of group Periph_DMA_DMA_STATUS_Bits */
N
N/** @} */ /* End of group Periph_DMA_Defines */
N
N/** @defgroup Periph_DMA_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_DMA_DMA_CFG_Bits DMA_CFG
N  * @{
N  */
N
N#define DMA_CFG_MASTER_ENABLE_Pos               0
N#define DMA_CFG_MASTER_ENABLE                   ((uint32_t)0x00000001)
N
N#define DMA_CFG_CHNL_PROT_CTRL_Pos              5
N#define DMA_CFG_CHNL_PROT_CTRL_Msk              ((uint32_t)0x000000E0)
N
N
N/** @} */ /* End of group Periph_DMA_DMA_CFG_Bits */
N
N/** @} */ /* End of group Periph_DMA_Defines */
N
N/** @} */ /* End of group Periph_DMA */
N
N/** @} */ /* End of group __1901BC1F_Peripheral_Units */
N
N/** @} */ /* End of group __CMSIS */
N
N#endif /* __1901BC1F_DMA_DEFS_H */
N
N/******************* (C) COPYRIGHT 2010 Phyton *********************************
N*
N* END OF FILE 1901BC1F_dma_defs.h */
L 98 ".\inc\1901BC1F.h" 2
N#include "1901BC1F_uart_defs.h"
L 1 ".\inc\1901BC1F_uart_defs.h" 1
N/**
N  ******************************************************************************
N  * @file    1901BC1F_uart_defs.h
N  * @author  Phyton Application Team
N  * @version V1.0.0
N  * @date    14/01/2011
N  * @brief   This file contains all the Special Function Registers definitions
N  *          for the UART peripheral unit used in the Milandr 1901BC1F
N  *          microcontrollers.
N  ******************************************************************************
N  * @copy
N  *
N  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
N  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
N  * TIME. AS A RESULT, PHYTON SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
N  * OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
N  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
N  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
N  *
N  * <h2><center>&copy; COPYRIGHT 2010 Phyton</center></h2>
N  ******************************************************************************
N  * FILE 1901BC1F_uart_defs.h
N  */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __1901BC1F_UART_DEFS_H
N#define __1901BC1F_UART_DEFS_H
N
N/** @addtogroup __CMSIS CMSIS
N  * @{
N  */
N
N/** @addtogroup __1901BC1F_Peripheral_Units 1901BC1F Peripheral Units
N  * @{
N  */
N
N/** @defgroup Periph_UART UART
N  * @{
N  */
N
N/** @defgroup Periph_UART_Data_Structures Data Structures
N  * @{
N  */
N
N/** @defgroup Periph_UART_TypeDef UART_TypeDef
N  * @{
N  */
N
Ntypedef struct
N{
N  __IO uint32_t DR;
X  volatile uint32_t DR;
N  __IO uint32_t RSR_ECR;
X  volatile uint32_t RSR_ECR;
N       uint32_t RESERVED0[4];
N  __IO uint32_t FR;
X  volatile uint32_t FR;
N       uint32_t RESERVED1;
N  __IO uint32_t ILPR;
X  volatile uint32_t ILPR;
N  __IO uint32_t IBRD;
X  volatile uint32_t IBRD;
N  __IO uint32_t FBRD;
X  volatile uint32_t FBRD;
N  __IO uint32_t LCR_H;
X  volatile uint32_t LCR_H;
N  __IO uint32_t CR;
X  volatile uint32_t CR;
N  __IO uint32_t IFLS;
X  volatile uint32_t IFLS;
N  __IO uint32_t IMSC;
X  volatile uint32_t IMSC;
N  __IO uint32_t RIS;
X  volatile uint32_t RIS;
N  __IO uint32_t MIS;
X  volatile uint32_t MIS;
N  __IO uint32_t ICR;
X  volatile uint32_t ICR;
N  __IO uint32_t DMACR;
X  volatile uint32_t DMACR;
N}UART_TypeDef;
N
N/** @} */ /* End of group Periph_UART_TypeDef */
N
N/** @} */ /* End of group Periph_UART_Data_Structures */
N
N/** @defgroup Periph_UART_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_UART_UART_DR_Bits UART_DR
N  * @{
N  */
N
N#define UART_DR_DATA_Pos                        0
N#define UART_DR_DATA_Msk                        ((uint32_t)0x000000FF)
N
N#define UART_DR_FE_Pos                          8
N#define UART_DR_FE                              ((uint32_t)0x00000100)
N
N#define UART_DR_PE_Pos                          9
N#define UART_DR_PE                              ((uint32_t)0x00000200)
N
N#define UART_DR_BE_Pos                          10
N#define UART_DR_BE                              ((uint32_t)0x00000400)
N
N#define UART_DR_OE_Pos                          11
N#define UART_DR_OE                              ((uint32_t)0x00000800)
N
N
N/** @} */ /* End of group Periph_UART_UART_DR_Bits */
N
N/** @} */ /* End of group Periph_UART_Defines */
N
N/** @defgroup Periph_UART_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_UART_UART_RSR_ECR_Bits UART_RSR_ECR
N  * @{
N  */
N
N#define UART_RSR_ECR_FE_Pos                     0
N#define UART_RSR_ECR_FE                         ((uint32_t)0x00000001)
N
N#define UART_RSR_ECR_PE_Pos                     1
N#define UART_RSR_ECR_PE                         ((uint32_t)0x00000002)
N
N#define UART_RSR_ECR_BE_Pos                     2
N#define UART_RSR_ECR_BE                         ((uint32_t)0x00000004)
N
N#define UART_RSR_ECR_OE_Pos                     3
N#define UART_RSR_ECR_OE                         ((uint32_t)0x00000008)
N
N
N/** @} */ /* End of group Periph_UART_UART_RSR_ECR_Bits */
N
N/** @} */ /* End of group Periph_UART_Defines */
N
N/** @defgroup Periph_UART_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_UART_UART_FR_Bits UART_FR
N  * @{
N  */
N
N#define UART_FR_CTS_Pos                         0
N#define UART_FR_CTS                             ((uint32_t)0x00000001)
N
N#define UART_FR_DSR_Pos                         1
N#define UART_FR_DSR                             ((uint32_t)0x00000002)
N
N#define UART_FR_DCD_Pos                         2
N#define UART_FR_DCD                             ((uint32_t)0x00000004)
N
N#define UART_FR_BUSY_Pos                        3
N#define UART_FR_BUSY                            ((uint32_t)0x00000008)
N
N#define UART_FR_RXFE_Pos                        4
N#define UART_FR_RXFE                            ((uint32_t)0x00000010)
N
N#define UART_FR_TXFF_Pos                        5
N#define UART_FR_TXFF                            ((uint32_t)0x00000020)
N
N#define UART_FR_RXFF_Pos                        6
N#define UART_FR_RXFF                            ((uint32_t)0x00000040)
N
N#define UART_FR_TXFE_Pos                        7
N#define UART_FR_TXFE                            ((uint32_t)0x00000080)
N
N#define UART_FR_RI_Pos                          8
N#define UART_FR_RI                              ((uint32_t)0x00000100)
N
N
N/** @} */ /* End of group Periph_UART_UART_FR_Bits */
N
N/** @} */ /* End of group Periph_UART_Defines */
N
N/** @defgroup Periph_UART_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_UART_UART_LCR_H_Bits UART_LCR_H
N  * @{
N  */
N
N#define UART_LCR_H_BRK_Pos                      0
N#define UART_LCR_H_BRK                          ((uint32_t)0x00000001)
N
N#define UART_LCR_H_PEN_Pos                      1
N#define UART_LCR_H_PEN                          ((uint32_t)0x00000002)
N
N#define UART_LCR_H_EPS_Pos                      2
N#define UART_LCR_H_EPS                          ((uint32_t)0x00000004)
N
N#define UART_LCR_H_STP2_Pos                     3
N#define UART_LCR_H_STP2                         ((uint32_t)0x00000008)
N
N#define UART_LCR_H_FEN_Pos                      4
N#define UART_LCR_H_FEN                          ((uint32_t)0x00000010)
N
N#define UART_LCR_H_WLEN_Pos                     5
N#define UART_LCR_H_WLEN_Msk                     ((uint32_t)0x00000060)
N
N#define UART_LCR_H_SPS_Pos                      7
N#define UART_LCR_H_SPS                          ((uint32_t)0x00000080)
N
N
N/** @} */ /* End of group Periph_UART_UART_LCR_H_Bits */
N
N/** @} */ /* End of group Periph_UART_Defines */
N
N/** @defgroup Periph_UART_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_UART_UART_CR_Bits UART_CR
N  * @{
N  */
N
N#define UART_CR_UARTEN_Pos                      0
N#define UART_CR_UARTEN                          ((uint32_t)0x00000001)
N
N#define UART_CR_SIREN_Pos                       1
N#define UART_CR_SIREN                           ((uint32_t)0x00000002)
N
N#define UART_CR_SIRLP_Pos                       2
N#define UART_CR_SIRLP                           ((uint32_t)0x00000004)
N
N#define UART_CR_LBE_Pos                         7
N#define UART_CR_LBE                             ((uint32_t)0x00000080)
N
N#define UART_CR_TXE_Pos                         8
N#define UART_CR_TXE                             ((uint32_t)0x00000100)
N
N#define UART_CR_RXE_Pos                         9
N#define UART_CR_RXE                             ((uint32_t)0x00000200)
N
N#define UART_CR_DTR_Pos                         10
N#define UART_CR_DTR                             ((uint32_t)0x00000400)
N
N#define UART_CR_RTS_Pos                         11
N#define UART_CR_RTS                             ((uint32_t)0x00000800)
N
N#define UART_CR_Out1_Pos                        12
N#define UART_CR_Out1                            ((uint32_t)0x00001000)
N
N#define UART_CR_Out2_Pos                        13
N#define UART_CR_Out2                            ((uint32_t)0x00002000)
N
N#define UART_CR_RTSEn_Pos                       14
N#define UART_CR_RTSEn                           ((uint32_t)0x00004000)
N
N#define UART_CR_CTSEn_Pos                       15
N#define UART_CR_CTSEn                           ((uint32_t)0x00008000)
N
N
N/** @} */ /* End of group Periph_UART_UART_CR_Bits */
N
N/** @} */ /* End of group Periph_UART_Defines */
N
N/** @defgroup Periph_UART_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_UART_UART_IFLS_Bits UART_IFLS
N  * @{
N  */
N
N#define UART_IFLS_TXIFLSEL_Pos                  0
N#define UART_IFLS_TXIFLSEL_Msk                  ((uint32_t)0x00000007)
N
N#define UART_IFLS_RXIFLSEL_Pos                  3
N#define UART_IFLS_RXIFLSEL_Msk                  ((uint32_t)0x00000038)
N
N
N/** @} */ /* End of group Periph_UART_UART_IFLS_Bits */
N
N/** @} */ /* End of group Periph_UART_Defines */
N
N/** @defgroup Periph_UART_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_UART_UART_IMSC_Bits UART_IMSC
N  * @{
N  */
N
N#define UART_IMSC_RIMIM_Pos                     0
N#define UART_IMSC_RIMIM                         ((uint32_t)0x00000001)
N
N#define UART_IMSC_CTSMIM_Pos                    1
N#define UART_IMSC_CTSMIM                        ((uint32_t)0x00000002)
N
N#define UART_IMSC_DCDMIM_Pos                    2
N#define UART_IMSC_DCDMIM                        ((uint32_t)0x00000004)
N
N#define UART_IMSC_DSRMIM_Pos                    3
N#define UART_IMSC_DSRMIM                        ((uint32_t)0x00000008)
N
N#define UART_IMSC_RXIM_Pos                      4
N#define UART_IMSC_RXIM                          ((uint32_t)0x00000010)
N
N#define UART_IMSC_TXIM_Pos                      5
N#define UART_IMSC_TXIM                          ((uint32_t)0x00000020)
N
N#define UART_IMSC_RTIM_Pos                      6
N#define UART_IMSC_RTIM                          ((uint32_t)0x00000040)
N
N#define UART_IMSC_FEIM_Pos                      7
N#define UART_IMSC_FEIM                          ((uint32_t)0x00000080)
N
N#define UART_IMSC_PEIM_Pos                      8
N#define UART_IMSC_PEIM                          ((uint32_t)0x00000100)
N
N#define UART_IMSC_BEIM_Pos                      9
N#define UART_IMSC_BEIM                          ((uint32_t)0x00000200)
N
N#define UART_IMSC_OEIM_Pos                      10
N#define UART_IMSC_OEIM                          ((uint32_t)0x00000400)
N
N
N/** @} */ /* End of group Periph_UART_UART_IMSC_Bits */
N
N/** @} */ /* End of group Periph_UART_Defines */
N
N/** @defgroup Periph_UART_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_UART_UART_RIS_Bits UART_RIS
N  * @{
N  */
N
N#define UART_RIS_RIRMIS_Pos                     0
N#define UART_RIS_RIRMIS                         ((uint32_t)0x00000001)
N
N#define UART_RIS_CTSRMIS_Pos                    1
N#define UART_RIS_CTSRMIS                        ((uint32_t)0x00000002)
N
N#define UART_RIS_DCDRMIS_Pos                    2
N#define UART_RIS_DCDRMIS                        ((uint32_t)0x00000004)
N
N#define UART_RIS_DSRRMIS_Pos                    3
N#define UART_RIS_DSRRMIS                        ((uint32_t)0x00000008)
N
N#define UART_RIS_RXRIS_Pos                      4
N#define UART_RIS_RXRIS                          ((uint32_t)0x00000010)
N
N#define UART_RIS_TXRIS_Pos                      5
N#define UART_RIS_TXRIS                          ((uint32_t)0x00000020)
N
N#define UART_RIS_RTRIS_Pos                      6
N#define UART_RIS_RTRIS                          ((uint32_t)0x00000040)
N
N#define UART_RIS_FERIS_Pos                      7
N#define UART_RIS_FERIS                          ((uint32_t)0x00000080)
N
N#define UART_RIS_PERIS_Pos                      8
N#define UART_RIS_PERIS                          ((uint32_t)0x00000100)
N
N#define UART_RIS_BERIS_Pos                      9
N#define UART_RIS_BERIS                          ((uint32_t)0x00000200)
N
N#define UART_RIS_OERIS_Pos                      10
N#define UART_RIS_OERIS                          ((uint32_t)0x00000400)
N
N
N/** @} */ /* End of group Periph_UART_UART_RIS_Bits */
N
N/** @} */ /* End of group Periph_UART_Defines */
N
N/** @defgroup Periph_UART_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_UART_UART_MIS_Bits UART_MIS
N  * @{
N  */
N
N#define UART_MIS_RIMMIS_Pos                     0
N#define UART_MIS_RIMMIS                         ((uint32_t)0x00000001)
N
N#define UART_MIS_CTSMMIS_Pos                    1
N#define UART_MIS_CTSMMIS                        ((uint32_t)0x00000002)
N
N#define UART_MIS_DCDMMIS_Pos                    2
N#define UART_MIS_DCDMMIS                        ((uint32_t)0x00000004)
N
N#define UART_MIS_DSRMMIS_Pos                    3
N#define UART_MIS_DSRMMIS                        ((uint32_t)0x00000008)
N
N#define UART_MIS_RXMIS_Pos                      4
N#define UART_MIS_RXMIS                          ((uint32_t)0x00000010)
N
N#define UART_MIS_TXMIS_Pos                      5
N#define UART_MIS_TXMIS                          ((uint32_t)0x00000020)
N
N#define UART_MIS_RTMIS_Pos                      6
N#define UART_MIS_RTMIS                          ((uint32_t)0x00000040)
N
N#define UART_MIS_FEMIS_Pos                      7
N#define UART_MIS_FEMIS                          ((uint32_t)0x00000080)
N
N#define UART_MIS_PEMIS_Pos                      8
N#define UART_MIS_PEMIS                          ((uint32_t)0x00000100)
N
N#define UART_MIS_BEMIS_Pos                      9
N#define UART_MIS_BEMIS                          ((uint32_t)0x00000200)
N
N#define UART_MIS_OEMIS_Pos                      10
N#define UART_MIS_OEMIS                          ((uint32_t)0x00000400)
N
N
N/** @} */ /* End of group Periph_UART_UART_MIS_Bits */
N
N/** @} */ /* End of group Periph_UART_Defines */
N
N/** @defgroup Periph_UART_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_UART_UART_ICR_Bits UART_ICR
N  * @{
N  */
N
N#define UART_ICR_RIMIC_Pos                      0
N#define UART_ICR_RIMIC                          ((uint32_t)0x00000001)
N
N#define UART_ICR_CTSMIC_Pos                     1
N#define UART_ICR_CTSMIC                         ((uint32_t)0x00000002)
N
N#define UART_ICR_DCDMIC_Pos                     2
N#define UART_ICR_DCDMIC                         ((uint32_t)0x00000004)
N
N#define UART_ICR_DSRMIC_Pos                     3
N#define UART_ICR_DSRMIC                         ((uint32_t)0x00000008)
N
N#define UART_ICR_RXIC_Pos                       4
N#define UART_ICR_RXIC                           ((uint32_t)0x00000010)
N
N#define UART_ICR_TXIC_Pos                       5
N#define UART_ICR_TXIC                           ((uint32_t)0x00000020)
N
N#define UART_ICR_RTIC_Pos                       6
N#define UART_ICR_RTIC                           ((uint32_t)0x00000040)
N
N#define UART_ICR_FEIC_Pos                       7
N#define UART_ICR_FEIC                           ((uint32_t)0x00000080)
N
N#define UART_ICR_PEIC_Pos                       8
N#define UART_ICR_PEIC                           ((uint32_t)0x00000100)
N
N#define UART_ICR_BEIC_Pos                       9
N#define UART_ICR_BEIC                           ((uint32_t)0x00000200)
N
N#define UART_ICR_OEIC_Pos                       10
N#define UART_ICR_OEIC                           ((uint32_t)0x00000400)
N
N
N/** @} */ /* End of group Periph_UART_UART_ICR_Bits */
N
N/** @} */ /* End of group Periph_UART_Defines */
N
N/** @defgroup Periph_UART_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_UART_UART_DMACR_Bits UART_DMACR
N  * @{
N  */
N
N#define UART_DMACR_RXDMAE_Pos                   0
N#define UART_DMACR_RXDMAE                       ((uint32_t)0x00000001)
N
N#define UART_DMACR_TXDMAE_Pos                   1
N#define UART_DMACR_TXDMAE                       ((uint32_t)0x00000002)
N
N#define UART_DMACR_DMAONERR_Pos                 2
N#define UART_DMACR_DMAONERR                     ((uint32_t)0x00000004)
N
N
N/** @} */ /* End of group Periph_UART_UART_DMACR_Bits */
N
N/** @} */ /* End of group Periph_UART_Defines */
N
N/** @} */ /* End of group Periph_UART */
N
N/** @} */ /* End of group __1901BC1F_Peripheral_Units */
N
N/** @} */ /* End of group __CMSIS */
N
N#endif /* __1901BC1F_UART_DEFS_H */
N
N/******************* (C) COPYRIGHT 2010 Phyton *********************************
N*
N* END OF FILE 1901BC1F_uart_defs.h */
L 99 ".\inc\1901BC1F.h" 2
N#include "1901BC1F_sdio_defs.h"
L 1 ".\inc\1901BC1F_sdio_defs.h" 1
N/**
N  ******************************************************************************
N  * @file    1901BC1F_sdio_defs.h
N  * @author  Phyton Application Team
N  * @version V1.0.0
N  * @date    14/01/2011
N  * @brief   This file contains all the Special Function Registers definitions
N  *          for the SDIO peripheral unit used in the Milandr 1901BC1F
N  *          microcontrollers.
N  ******************************************************************************
N  * @copy
N  *
N  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
N  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
N  * TIME. AS A RESULT, PHYTON SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
N  * OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
N  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
N  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
N  *
N  * <h2><center>&copy; COPYRIGHT 2010 Phyton</center></h2>
N  ******************************************************************************
N  * FILE 1901BC1F_sdio_defs.h
N  */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __1901BC1F_SDIO_DEFS_H
N#define __1901BC1F_SDIO_DEFS_H
N
N/** @addtogroup __CMSIS CMSIS
N  * @{
N  */
N
N/** @addtogroup __1901BC1F_Peripheral_Units 1901BC1F Peripheral Units
N  * @{
N  */
N
N/** @defgroup Periph_SDIO SDIO
N  * @{
N  */
N
N/** @defgroup Periph_SDIO_Data_Structures Data Structures
N  * @{
N  */
N
N/** @defgroup Periph_SDIO_TypeDef SDIO_TypeDef
N  * @{
N  */
N
Ntypedef struct
N{
N  __IO uint32_t SD_CR;
X  volatile uint32_t SD_CR;
N  __IO uint32_t SD_SR;
X  volatile uint32_t SD_SR;
N  __IO uint32_t SD_CMDDR;
X  volatile uint32_t SD_CMDDR;
N  __IO uint32_t SD_DATDR;
X  volatile uint32_t SD_DATDR;
N  __IO uint32_t SD_CMDCRC;
X  volatile uint32_t SD_CMDCRC;
N  __IO uint32_t SD_DATA0CRC;
X  volatile uint32_t SD_DATA0CRC;
N  __IO uint32_t SD_DATA1CRC;
X  volatile uint32_t SD_DATA1CRC;
N  __IO uint32_t SD_DATA2CRC;
X  volatile uint32_t SD_DATA2CRC;
N  __IO uint32_t SD_DATA3CRC;
X  volatile uint32_t SD_DATA3CRC;
N  __IO uint32_t SD_CMDtransfer;
X  volatile uint32_t SD_CMDtransfer;
N  __IO uint32_t SD_DATtransfer;
X  volatile uint32_t SD_DATtransfer;
N}SDIO_TypeDef;
N
N/** @} */ /* End of group Periph_SDIO_TypeDef */
N
N/** @} */ /* End of group Periph_SDIO_Data_Structures */
N
N/** @defgroup Periph_SDIO_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_SDIO_SDIO_SD_CR_Bits SDIO_SD_CR
N  * @{
N  */
N
N#define SDIO_SD_CR_DIRCMD_Pos                   0
N#define SDIO_SD_CR_DIRCMD                       ((uint32_t)0x00000001)
N
N#define SDIO_SD_CR_DIRDAT_Pos                   1
N#define SDIO_SD_CR_DIRDAT                       ((uint32_t)0x00000002)
N
N#define SDIO_SD_CR_WORK_Pos                     2
N#define SDIO_SD_CR_WORK                         ((uint32_t)0x00000004)
N
N#define SDIO_SD_CR_SBITCMD_Pos                  3
N#define SDIO_SD_CR_SBITCMD                      ((uint32_t)0x00000008)
N
N#define SDIO_SD_CR_SBITDAT_Pos                  4
N#define SDIO_SD_CR_SBITDAT                      ((uint32_t)0x00000010)
N
N#define SDIO_SD_CR_BR0_Pos                      5
N#define SDIO_SD_CR_BR0                          ((uint32_t)0x00000020)
N
N#define SDIO_SD_CR_BR1_Pos                      6
N#define SDIO_SD_CR_BR1                          ((uint32_t)0x00000040)
N
N#define SDIO_SD_CR_BR2_Pos                      7
N#define SDIO_SD_CR_BR2                          ((uint32_t)0x00000080)
N
N#define SDIO_SD_CR_CRCEN_DAT_Pos                8
N#define SDIO_SD_CR_CRCEN_DAT                    ((uint32_t)0x00000100)
N
N#define SDIO_SD_CR_CRCEN_CMD_Pos                9
N#define SDIO_SD_CR_CRCEN_CMD                    ((uint32_t)0x00000200)
N
N#define SDIO_SD_CR_TXEIE_DAT_Pos                10
N#define SDIO_SD_CR_TXEIE_DAT                    ((uint32_t)0x00000400)
N
N#define SDIO_SD_CR_RXNEIE_DAT_Pos               11
N#define SDIO_SD_CR_RXNEIE_DAT                   ((uint32_t)0x00000800)
N
N#define SDIO_SD_CR_RXFIE_DAT_Pos                12
N#define SDIO_SD_CR_RXFIE_DAT                    ((uint32_t)0x00001000)
N
N#define SDIO_SD_CR_TXEIE_CMD_Pos                13
N#define SDIO_SD_CR_TXEIE_CMD                    ((uint32_t)0x00002000)
N
N#define SDIO_SD_CR_RXNEIE_CMD_Pos               14
N#define SDIO_SD_CR_RXNEIE_CMD                   ((uint32_t)0x00004000)
N
N#define SDIO_SD_CR_RXFIE_CMD_Pos                15
N#define SDIO_SD_CR_RXFIE_CMD                    ((uint32_t)0x00008000)
N
N#define SDIO_SD_CR_WIDTHDAT_Pos                 16
N#define SDIO_SD_CR_WIDTHDAT                     ((uint32_t)0x00010000)
N
N#define SDIO_SD_CR_WRITECMD_Pos                 17
N#define SDIO_SD_CR_WRITECMD                     ((uint32_t)0x00020000)
N
N#define SDIO_SD_CR_ENDBUSY_Pos                  18
N#define SDIO_SD_CR_ENDBUSY                      ((uint32_t)0x00040000)
N
N#define SDIO_SD_CR_WORK2_Pos                    19
N#define SDIO_SD_CR_WORK2                        ((uint32_t)0x00080000)
N
N#define SDIO_SD_CR_CLKOE_Pos                    20
N#define SDIO_SD_CR_CLKOE                        ((uint32_t)0x00100000)
N
N
N/** @} */ /* End of group Periph_SDIO_SDIO_SD_CR_Bits */
N
N/** @} */ /* End of group Periph_SDIO_Defines */
N
N/** @defgroup Periph_SDIO_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_SDIO_SDIO_SD_SR_Bits SDIO_SD_SR
N  * @{
N  */
N
N#define SDIO_SD_SR_FIFODAT_FULL_Pos             0
N#define SDIO_SD_SR_FIFODAT_FULL                 ((uint32_t)0x00000001)
N
N#define SDIO_SD_SR_FIFOCMD_FULL_Pos             1
N#define SDIO_SD_SR_FIFOCMD_FULL                 ((uint32_t)0x00000002)
N
N#define SDIO_SD_SR_FIFODAT_EMPTY_Pos            2
N#define SDIO_SD_SR_FIFODAT_EMPTY                ((uint32_t)0x00000004)
N
N#define SDIO_SD_SR_FIFOCMD_EMPTY_Pos            3
N#define SDIO_SD_SR_FIFOCMD_EMPTY                ((uint32_t)0x00000008)
N
N
N/** @} */ /* End of group Periph_SDIO_SDIO_SD_SR_Bits */
N
N/** @} */ /* End of group Periph_SDIO_Defines */
N
N/** @} */ /* End of group Periph_SDIO */
N
N/** @} */ /* End of group __1901BC1F_Peripheral_Units */
N
N/** @} */ /* End of group __CMSIS */
N
N#endif /* __1901BC1F_SDIO_DEFS_H */
N
N/******************* (C) COPYRIGHT 2010 Phyton *********************************
N*
N* END OF FILE 1901BC1F_sdio_defs.h */
L 100 ".\inc\1901BC1F.h" 2
N#include "1901BC1F_i2c_defs.h"
L 1 ".\inc\1901BC1F_i2c_defs.h" 1
N/**
N  ******************************************************************************
N  * @file    1901BC1F_i2c_defs.h
N  * @author  Phyton Application Team
N  * @version V1.0.0
N  * @date    14/01/2011
N  * @brief   This file contains all the Special Function Registers definitions
N  *          for the I2C peripheral unit used in the Milandr 1901BC1F
N  *          microcontrollers.
N  ******************************************************************************
N  * @copy
N  *
N  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
N  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
N  * TIME. AS A RESULT, PHYTON SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
N  * OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
N  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
N  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
N  *
N  * <h2><center>&copy; COPYRIGHT 2010 Phyton</center></h2>
N  ******************************************************************************
N  * FILE 1901BC1F_i2c_defs.h
N  */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __1901BC1F_I2C_DEFS_H
N#define __1901BC1F_I2C_DEFS_H
N
N/** @addtogroup __CMSIS CMSIS
N  * @{
N  */
N
N/** @addtogroup __1901BC1F_Peripheral_Units 1901BC1F Peripheral Units
N  * @{
N  */
N
N/** @defgroup Periph_I2C I2C
N  * @{
N  */
N
N/** @defgroup Periph_I2C_Data_Structures Data Structures
N  * @{
N  */
N
N/** @defgroup Periph_I2C_TypeDef I2C_TypeDef
N  * @{
N  */
N
Ntypedef struct
N{
N  __IO uint32_t PRL;
X  volatile uint32_t PRL;
N  __IO uint32_t PRP;
X  volatile uint32_t PRP;
N  __IO uint32_t CTR;
X  volatile uint32_t CTR;
N  __IO uint32_t RXD;
X  volatile uint32_t RXD;
N  __IO uint32_t STA;
X  volatile uint32_t STA;
N  __IO uint32_t TXD;
X  volatile uint32_t TXD;
N  __IO uint32_t CMD;
X  volatile uint32_t CMD;
N}I2C_TypeDef;
N
N/** @} */ /* End of group Periph_I2C_TypeDef */
N
N/** @} */ /* End of group Periph_I2C_Data_Structures */
N
N/** @defgroup Periph_I2C_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_I2C_I2C_CTR_Bits I2C_CTR
N  * @{
N  */
N
N#define I2C_CTR_S_I2C_Pos                       0
N#define I2C_CTR_S_I2C                           ((uint32_t)0x00000001)
N
N#define I2C_CTR_EN_INT_Pos                      1
N#define I2C_CTR_EN_INT                          ((uint32_t)0x00000002)
N
N#define I2C_CTR_EN_I2C_Pos                      2
N#define I2C_CTR_EN_I2C                          ((uint32_t)0x00000004)
N
N
N/** @} */ /* End of group Periph_I2C_I2C_CTR_Bits */
N
N/** @} */ /* End of group Periph_I2C_Defines */
N
N/** @defgroup Periph_I2C_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_I2C_I2C_STA_Bits I2C_STA
N  * @{
N  */
N
N#define I2C_STA_INT_Pos                         0
N#define I2C_STA_INT                             ((uint32_t)0x00000001)
N
N#define I2C_STA_TR_PROG_Pos                     1
N#define I2C_STA_TR_PROG                         ((uint32_t)0x00000002)
N
N#define I2C_STA_LOST_ARB_Pos                    5
N#define I2C_STA_LOST_ARB                        ((uint32_t)0x00000020)
N
N#define I2C_STA_BUSY_Pos                        6
N#define I2C_STA_BUSY                            ((uint32_t)0x00000040)
N
N#define I2C_STA_Rx_ACK_Pos                      7
N#define I2C_STA_Rx_ACK                          ((uint32_t)0x00000080)
N
N
N/** @} */ /* End of group Periph_I2C_I2C_STA_Bits */
N
N/** @} */ /* End of group Periph_I2C_Defines */
N
N/** @defgroup Periph_I2C_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_I2C_I2C_CMD_Bits I2C_CMD
N  * @{
N  */
N
N#define I2C_CMD_CLRINT_Pos                      0
N#define I2C_CMD_CLRINT                          ((uint32_t)0x00000001)
N
N#define I2C_CMD_ACK_Pos                         3
N#define I2C_CMD_ACK                             ((uint32_t)0x00000008)
N
N#define I2C_CMD_WR_Pos                          4
N#define I2C_CMD_WR                              ((uint32_t)0x00000010)
N
N#define I2C_CMD_RD_Pos                          5
N#define I2C_CMD_RD                              ((uint32_t)0x00000020)
N
N#define I2C_CMD_STOP_Pos                        6
N#define I2C_CMD_STOP                            ((uint32_t)0x00000040)
N
N#define I2C_CMD_START_Pos                       7
N#define I2C_CMD_START                           ((uint32_t)0x00000080)
N
N
N/** @} */ /* End of group Periph_I2C_I2C_CMD_Bits */
N
N/** @} */ /* End of group Periph_I2C_Defines */
N
N/** @} */ /* End of group Periph_I2C */
N
N/** @} */ /* End of group __1901BC1F_Peripheral_Units */
N
N/** @} */ /* End of group __CMSIS */
N
N#endif /* __1901BC1F_I2C_DEFS_H */
N
N/******************* (C) COPYRIGHT 2010 Phyton *********************************
N*
N* END OF FILE 1901BC1F_i2c_defs.h */
L 101 ".\inc\1901BC1F.h" 2
N#include "1901BC1F_power_defs.h"
L 1 ".\inc\1901BC1F_power_defs.h" 1
N/**
N  ******************************************************************************
N  * @file    1901BC1F_power_defs.h
N  * @author  Phyton Application Team
N  * @version V1.0.0
N  * @date    14/01/2011
N  * @brief   This file contains all the Special Function Registers definitions
N  *          for the POWER peripheral unit used in the Milandr 1901BC1F
N  *          microcontrollers.
N  ******************************************************************************
N  * @copy
N  *
N  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
N  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
N  * TIME. AS A RESULT, PHYTON SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
N  * OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
N  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
N  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
N  *
N  * <h2><center>&copy; COPYRIGHT 2010 Phyton</center></h2>
N  ******************************************************************************
N  * FILE 1901BC1F_power_defs.h
N  */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __1901BC1F_POWER_DEFS_H
N#define __1901BC1F_POWER_DEFS_H
N
N/** @addtogroup __CMSIS CMSIS
N  * @{
N  */
N
N/** @addtogroup __1901BC1F_Peripheral_Units 1901BC1F Peripheral Units
N  * @{
N  */
N
N/** @defgroup Periph_POWER POWER
N  * @{
N  */
N
N/** @defgroup Periph_POWER_Data_Structures Data Structures
N  * @{
N  */
N
N/** @defgroup Periph_POWER_TypeDef POWER_TypeDef
N  * @{
N  */
N
Ntypedef struct
N{
N  __IO uint32_t PVDCS;
X  volatile uint32_t PVDCS;
N}POWER_TypeDef;
N
N/** @} */ /* End of group Periph_POWER_TypeDef */
N
N/** @} */ /* End of group Periph_POWER_Data_Structures */
N
N/** @defgroup Periph_POWER_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_POWER_POWER_PVDCS_Bits POWER_PVDCS
N  * @{
N  */
N
N#define POWER_PVDCS_PVDEN_Pos                   0
N#define POWER_PVDCS_PVDEN                       ((uint32_t)0x00000001)
N
N#define POWER_PVDCS_PBLS_Pos                    1
N#define POWER_PVDCS_PBLS_Msk                    ((uint32_t)0x00000006)
N
N#define POWER_PVDCS_PLS_Pos                     3
N#define POWER_PVDCS_PLS_Msk                     ((uint32_t)0x00000038)
N
N#define POWER_PVDCS_PVBD_Pos                    6
N#define POWER_PVDCS_PVBD                        ((uint32_t)0x00000040)
N
N#define POWER_PVDCS_PVD_Pos                     7
N#define POWER_PVDCS_PVD                         ((uint32_t)0x00000080)
N
N#define POWER_PVDCS_IEPVBD_Pos                  8
N#define POWER_PVDCS_IEPVBD                      ((uint32_t)0x00000100)
N
N#define POWER_PVDCS_IEPVD_Pos                   9
N#define POWER_PVDCS_IEPVD                       ((uint32_t)0x00000200)
N
N#define POWER_PVDCS_INVB_Pos                    10
N#define POWER_PVDCS_INVB                        ((uint32_t)0x00000400)
N
N#define POWER_PVDCS_INV_Pos                     11
N#define POWER_PVDCS_INV                         ((uint32_t)0x00000800)
N
N
N/** @} */ /* End of group Periph_POWER_POWER_PVDCS_Bits */
N
N/** @} */ /* End of group Periph_POWER_Defines */
N
N/** @} */ /* End of group Periph_POWER */
N
N/** @} */ /* End of group __1901BC1F_Peripheral_Units */
N
N/** @} */ /* End of group __CMSIS */
N
N#endif /* __1901BC1F_POWER_DEFS_H */
N
N/******************* (C) COPYRIGHT 2010 Phyton *********************************
N*
N* END OF FILE 1901BC1F_power_defs.h */
L 102 ".\inc\1901BC1F.h" 2
N#include "1901BC1F_wwdg_defs.h"
L 1 ".\inc\1901BC1F_wwdg_defs.h" 1
N/**
N  ******************************************************************************
N  * @file    1901BC1F_wwdg_defs.h
N  * @author  Phyton Application Team
N  * @version V1.0.0
N  * @date    14/01/2011
N  * @brief   This file contains all the Special Function Registers definitions
N  *          for the WWDG peripheral unit used in the Milandr 1901BC1F
N  *          microcontrollers.
N  ******************************************************************************
N  * @copy
N  *
N  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
N  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
N  * TIME. AS A RESULT, PHYTON SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
N  * OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
N  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
N  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
N  *
N  * <h2><center>&copy; COPYRIGHT 2010 Phyton</center></h2>
N  ******************************************************************************
N  * FILE 1901BC1F_wwdg_defs.h
N  */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __1901BC1F_WWDG_DEFS_H
N#define __1901BC1F_WWDG_DEFS_H
N
N/** @addtogroup __CMSIS CMSIS
N  * @{
N  */
N
N/** @addtogroup __1901BC1F_Peripheral_Units 1901BC1F Peripheral Units
N  * @{
N  */
N
N/** @defgroup Periph_WWDG WWDG
N  * @{
N  */
N
N/** @defgroup Periph_WWDG_Data_Structures Data Structures
N  * @{
N  */
N
N/** @defgroup Periph_WWDG_TypeDef WWDG_TypeDef
N  * @{
N  */
N
Ntypedef struct
N{
N  __IO uint32_t CR;
X  volatile uint32_t CR;
N  __IO uint32_t CFR;
X  volatile uint32_t CFR;
N  __IO uint32_t SR;
X  volatile uint32_t SR;
N}WWDG_TypeDef;
N
N/** @} */ /* End of group Periph_WWDG_TypeDef */
N
N/** @} */ /* End of group Periph_WWDG_Data_Structures */
N
N/** @defgroup Periph_WWDG_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_WWDG_WWDG_CR_Bits WWDG_CR
N  * @{
N  */
N
N#define WWDG_CR_T_Pos                           0
N#define WWDG_CR_T_Msk                           ((uint32_t)0x0000007F)
N
N#define WWDG_CR_WDGA_Pos                        7
N#define WWDG_CR_WDGA                            ((uint32_t)0x00000080)
N
N
N/** @} */ /* End of group Periph_WWDG_WWDG_CR_Bits */
N
N/** @} */ /* End of group Periph_WWDG_Defines */
N
N/** @defgroup Periph_WWDG_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_WWDG_WWDG_CFR_Bits WWDG_CFR
N  * @{
N  */
N
N#define WWDG_CFR_W_Pos                          0
N#define WWDG_CFR_W_Msk                          ((uint32_t)0x0000007F)
N
N#define WWDG_CFR_WGTB_Pos                       7
N#define WWDG_CFR_WGTB_Msk                       ((uint32_t)0x00000180)
N
N#define WWDG_CFR_EWI_Pos                        9
N#define WWDG_CFR_EWI                            ((uint32_t)0x00000200)
N
N
N/** @} */ /* End of group Periph_WWDG_WWDG_CFR_Bits */
N
N/** @} */ /* End of group Periph_WWDG_Defines */
N
N/** @} */ /* End of group Periph_WWDG */
N
N/** @} */ /* End of group __1901BC1F_Peripheral_Units */
N
N/** @} */ /* End of group __CMSIS */
N
N#endif /* __1901BC1F_WWDG_DEFS_H */
N
N/******************* (C) COPYRIGHT 2010 Phyton *********************************
N*
N* END OF FILE 1901BC1F_wwdg_defs.h */
L 103 ".\inc\1901BC1F.h" 2
N#include "1901BC1F_iwdg_defs.h"
L 1 ".\inc\1901BC1F_iwdg_defs.h" 1
N/**
N  ******************************************************************************
N  * @file    1901BC1F_iwdg_defs.h
N  * @author  Phyton Application Team
N  * @version V1.0.0
N  * @date    14/01/2011
N  * @brief   This file contains all the Special Function Registers definitions
N  *          for the IWDG peripheral unit used in the Milandr 1901BC1F
N  *          microcontrollers.
N  ******************************************************************************
N  * @copy
N  *
N  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
N  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
N  * TIME. AS A RESULT, PHYTON SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
N  * OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
N  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
N  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
N  *
N  * <h2><center>&copy; COPYRIGHT 2010 Phyton</center></h2>
N  ******************************************************************************
N  * FILE 1901BC1F_iwdg_defs.h
N  */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __1901BC1F_IWDG_DEFS_H
N#define __1901BC1F_IWDG_DEFS_H
N
N/** @addtogroup __CMSIS CMSIS
N  * @{
N  */
N
N/** @addtogroup __1901BC1F_Peripheral_Units 1901BC1F Peripheral Units
N  * @{
N  */
N
N/** @defgroup Periph_IWDG IWDG
N  * @{
N  */
N
N/** @defgroup Periph_IWDG_Data_Structures Data Structures
N  * @{
N  */
N
N/** @defgroup Periph_IWDG_TypeDef IWDG_TypeDef
N  * @{
N  */
N
Ntypedef struct
N{
N  __IO uint32_t KR;
X  volatile uint32_t KR;
N  __IO uint32_t PR;
X  volatile uint32_t PR;
N  __IO uint32_t PRL;
X  volatile uint32_t PRL;
N  __IO uint32_t SR;
X  volatile uint32_t SR;
N}IWDG_TypeDef;
N
N/** @} */ /* End of group Periph_IWDG_TypeDef */
N
N/** @} */ /* End of group Periph_IWDG_Data_Structures */
N
N/** @defgroup Periph_IWDG_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_IWDG_IWDG_SR_Bits IWDG_SR
N  * @{
N  */
N
N#define IWDG_SR_PVU_Pos                         0
N#define IWDG_SR_PVU                             ((uint32_t)0x00000001)
N
N#define IWDG_SR_RVU_Pos                         1
N#define IWDG_SR_RVU                             ((uint32_t)0x00000002)
N
N
N/** @} */ /* End of group Periph_IWDG_IWDG_SR_Bits */
N
N/** @} */ /* End of group Periph_IWDG_Defines */
N
N/** @} */ /* End of group Periph_IWDG */
N
N/** @} */ /* End of group __1901BC1F_Peripheral_Units */
N
N/** @} */ /* End of group __CMSIS */
N
N#endif /* __1901BC1F_IWDG_DEFS_H */
N
N/******************* (C) COPYRIGHT 2010 Phyton *********************************
N*
N* END OF FILE 1901BC1F_iwdg_defs.h */
L 104 ".\inc\1901BC1F.h" 2
N#include "1901BC1F_timer_defs.h"
L 1 ".\inc\1901BC1F_timer_defs.h" 1
N/**
N  ******************************************************************************
N  * @file    1901BC1F_timer_defs.h
N  * @author  Phyton Application Team
N  * @version V1.0.0
N  * @date    14/01/2011
N  * @brief   This file contains all the Special Function Registers definitions
N  *          for the TIMER peripheral unit used in the Milandr 1901BC1F
N  *          microcontrollers.
N  ******************************************************************************
N  * @copy
N  *
N  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
N  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
N  * TIME. AS A RESULT, PHYTON SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
N  * OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
N  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
N  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
N  *
N  * <h2><center>&copy; COPYRIGHT 2010 Phyton</center></h2>
N  ******************************************************************************
N  * FILE 1901BC1F_timer_defs.h
N  */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __1901BC1F_TIMER_DEFS_H
N#define __1901BC1F_TIMER_DEFS_H
N
N/** @addtogroup __CMSIS CMSIS
N  * @{
N  */
N
N/** @addtogroup __1901BC1F_Peripheral_Units 1901BC1F Peripheral Units
N  * @{
N  */
N
N/** @defgroup Periph_TIMER TIMER
N  * @{
N  */
N
N/** @defgroup Periph_TIMER_Data_Structures Data Structures
N  * @{
N  */
N
N/** @defgroup Periph_TIMER_TypeDef TIMER_TypeDef
N  * @{
N  */
N
Ntypedef struct
N{
N  __IO uint32_t CNT;
X  volatile uint32_t CNT;
N  __IO uint32_t PSG;
X  volatile uint32_t PSG;
N  __IO uint32_t ARR;
X  volatile uint32_t ARR;
N  __IO uint32_t CNTRL;
X  volatile uint32_t CNTRL;
N  __IO uint32_t CCR1;
X  volatile uint32_t CCR1;
N  __IO uint32_t CCR2;
X  volatile uint32_t CCR2;
N  __IO uint32_t CCR3;
X  volatile uint32_t CCR3;
N  __IO uint32_t CCR4;
X  volatile uint32_t CCR4;
N  __IO uint32_t CH1_CNTRL;
X  volatile uint32_t CH1_CNTRL;
N  __IO uint32_t CH2_CNTRL;
X  volatile uint32_t CH2_CNTRL;
N  __IO uint32_t CH3_CNTRL;
X  volatile uint32_t CH3_CNTRL;
N  __IO uint32_t CH4_CNTRL;
X  volatile uint32_t CH4_CNTRL;
N  __IO uint32_t CH1_CNTRL1;
X  volatile uint32_t CH1_CNTRL1;
N  __IO uint32_t CH2_CNTRL1;
X  volatile uint32_t CH2_CNTRL1;
N  __IO uint32_t CH3_CNTRL1;
X  volatile uint32_t CH3_CNTRL1;
N  __IO uint32_t CH4_CNTRL1;
X  volatile uint32_t CH4_CNTRL1;
N  __IO uint32_t CH1_DTG;
X  volatile uint32_t CH1_DTG;
N  __IO uint32_t CH2_DTG;
X  volatile uint32_t CH2_DTG;
N  __IO uint32_t CH3_DTG;
X  volatile uint32_t CH3_DTG;
N  __IO uint32_t CH4_DTG;
X  volatile uint32_t CH4_DTG;
N  __IO uint32_t BRKETR_CNTRL;
X  volatile uint32_t BRKETR_CNTRL;
N  __IO uint32_t STATUS;
X  volatile uint32_t STATUS;
N  __IO uint32_t IE;
X  volatile uint32_t IE;
N  __IO uint32_t DMA_RE;
X  volatile uint32_t DMA_RE;
N  __IO uint32_t CH1_CNTRL2;
X  volatile uint32_t CH1_CNTRL2;
N  __IO uint32_t CH2_CNTRL2;
X  volatile uint32_t CH2_CNTRL2;
N  __IO uint32_t CH3_CNTRL2;
X  volatile uint32_t CH3_CNTRL2;
N  __IO uint32_t CH4_CNTRL2;
X  volatile uint32_t CH4_CNTRL2;
N  __IO uint32_t CCR11;
X  volatile uint32_t CCR11;
N  __IO uint32_t CCR21;
X  volatile uint32_t CCR21;
N  __IO uint32_t CCR31;
X  volatile uint32_t CCR31;
N  __IO uint32_t CCR41;
X  volatile uint32_t CCR41;
N}TIMER_TypeDef;
N
N/** @} */ /* End of group Periph_TIMER_TypeDef */
N
N/** @} */ /* End of group Periph_TIMER_Data_Structures */
N
N/** @defgroup Periph_TIMER_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_TIMER_TIMER_CNTRL_Bits TIMER_CNTRL
N  * @{
N  */
N
N#define TIMER_CNTRL_CNT_EN_Pos                  0
N#define TIMER_CNTRL_CNT_EN                      ((uint32_t)0x00000001)
N
N#define TIMER_CNTRL_ARRB_EN_Pos                 1
N#define TIMER_CNTRL_ARRB_EN                     ((uint32_t)0x00000002)
N
N#define TIMER_CNTRL_WR_CMPL_Pos                 2
N#define TIMER_CNTRL_WR_CMPL                     ((uint32_t)0x00000004)
N
N#define TIMER_CNTRL_DIR_Pos                     3
N#define TIMER_CNTRL_DIR                         ((uint32_t)0x00000008)
N
N#define TIMER_CNTRL_FDTS_Pos                    4
N#define TIMER_CNTRL_FDTS_Msk                    ((uint32_t)0x00000030)
N
N#define TIMER_CNTRL_CNT_MODE_Pos                6
N#define TIMER_CNTRL_CNT_MODE_Msk                ((uint32_t)0x000000C0)
N
N#define TIMER_CNTRL_EVENT_SEL_Pos               8
N#define TIMER_CNTRL_EVENT_SEL_Msk               ((uint32_t)0x00000F00)
N
N
N/** @} */ /* End of group Periph_TIMER_TIMER_CNTRL_Bits */
N
N/** @} */ /* End of group Periph_TIMER_Defines */
N
N/** @defgroup Periph_TIMER_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_TIMER_TIMER_CH_CNTRL_Bits TIMER_CH_CNTRL
N  * @{
N  */
N
N#define TIMER_CH_CNTRL_CHFLTR_Pos               0
N#define TIMER_CH_CNTRL_CHFLTR_Msk               ((uint32_t)0x0000000F)
N
N#define TIMER_CH_CNTRL_CHSEL_Pos                4
N#define TIMER_CH_CNTRL_CHSEL_Msk                ((uint32_t)0x00000030)
N
N#define TIMER_CH_CNTRL_CHPSC_Pos                6
N#define TIMER_CH_CNTRL_CHPSC_Msk                ((uint32_t)0x000000C0)
N
N#define TIMER_CH_CNTRL_OCCE_Pos                 8
N#define TIMER_CH_CNTRL_OCCE                     ((uint32_t)0x00000100)
N
N#define TIMER_CH_CNTRL_OCCM_Pos                 9
N#define TIMER_CH_CNTRL_OCCM_Msk                 ((uint32_t)0x00000E00)
N
N#define TIMER_CH_CNTRL_BRKEN_Pos                12
N#define TIMER_CH_CNTRL_BRKEN                    ((uint32_t)0x00001000)
N
N#define TIMER_CH_CNTRL_ETREN_Pos                13
N#define TIMER_CH_CNTRL_ETREN                    ((uint32_t)0x00002000)
N
N#define TIMER_CH_CNTRL_WR_CMPL_Pos              14
N#define TIMER_CH_CNTRL_WR_CMPL                  ((uint32_t)0x00004000)
N
N#define TIMER_CH_CNTRL_CAP_nPWM_Pos             15
N#define TIMER_CH_CNTRL_CAP_nPWM                 ((uint32_t)0x00008000)
N
N
N/** @} */ /* End of group Periph_TIMER_TIMER_CH_CNTRL_Bits */
N
N/** @} */ /* End of group Periph_TIMER_Defines */
N
N/** @defgroup Periph_TIMER_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_TIMER_TIMER_CH_CNTRL1_Bits TIMER_CH_CNTRL1
N  * @{
N  */
N
N#define TIMER_CH_CNTRL1_SELOE_Pos               0
N#define TIMER_CH_CNTRL1_SELOE_Msk               ((uint32_t)0x00000003)
N
N#define TIMER_CH_CNTRL1_SELO_Pos                2
N#define TIMER_CH_CNTRL1_SELO_Msk                ((uint32_t)0x0000000C)
N
N#define TIMER_CH_CNTRL1_INV_Pos                 4
N#define TIMER_CH_CNTRL1_INV                     ((uint32_t)0x00000010)
N
N#define TIMER_CH_CNTRL1_NSELOE_Pos              8
N#define TIMER_CH_CNTRL1_NSELOE_Msk              ((uint32_t)0x00000300)
N
N#define TIMER_CH_CNTRL1_NSELO_Pos               10
N#define TIMER_CH_CNTRL1_NSELO_Msk               ((uint32_t)0x00000C00)
N
N#define TIMER_CH_CNTRL1_NINV_Pos                12
N#define TIMER_CH_CNTRL1_NINV                    ((uint32_t)0x00001000)
N
N
N/** @} */ /* End of group Periph_TIMER_TIMER_CH_CNTRL1_Bits */
N
N/** @} */ /* End of group Periph_TIMER_Defines */
N
N/** @defgroup Periph_TIMER_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_TIMER_TIMER_CH_DTG_Bits TIMER_CH_DTG
N  * @{
N  */
N
N#define TIMER_CH_DTG_DTGx_Pos                   0
N#define TIMER_CH_DTG_DTGx_Msk                   ((uint32_t)0x0000000F)
N
N#define TIMER_CH_DTG_EDTS_Pos                   4
N#define TIMER_CH_DTG_EDTS                       ((uint32_t)0x00000010)
N
N#define TIMER_CH_DTG_Pos                        8
N#define TIMER_CH_DTG_Msk                        ((uint32_t)0x0000FF00)
N
N
N/** @} */ /* End of group Periph_TIMER_TIMER_CH_DTG_Bits */
N
N/** @} */ /* End of group Periph_TIMER_Defines */
N
N/** @defgroup Periph_TIMER_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_TIMER_TIMER_BRKETR_CNTRL_Bits TIMER_BRKETR_CNTRL
N  * @{
N  */
N
N#define TIMER_BRKETR_CNTRL_BRK_INV_Pos          0
N#define TIMER_BRKETR_CNTRL_BRK_INV              ((uint32_t)0x00000001)
N
N#define TIMER_BRKETR_CNTRL_ETR_INV_Pos          1
N#define TIMER_BRKETR_CNTRL_ETR_INV              ((uint32_t)0x00000002)
N
N#define TIMER_BRKETR_CNTRL_ETR_PSC_Pos          2
N#define TIMER_BRKETR_CNTRL_ETR_PSC_Msk          ((uint32_t)0x0000000C)
N
N#define TIMER_BRKETR_CNTRL_ETR_FILTER_Pos       4
N#define TIMER_BRKETR_CNTRL_ETR_FILTER_Msk       ((uint32_t)0x000000F0)
N
N
N/** @} */ /* End of group Periph_TIMER_TIMER_BRKETR_CNTRL_Bits */
N
N/** @} */ /* End of group Periph_TIMER_Defines */
N
N/** @defgroup Periph_TIMER_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_TIMER_TIMER_STATUS_Bits TIMER_STATUS
N  * @{
N  */
N
N#define TIMER_STATUS_CNT_ZERO_EVENT_Pos         0
N#define TIMER_STATUS_CNT_ZERO_EVENT             ((uint32_t)0x00000001)
N
N#define TIMER_STATUS_CNT_ARR_EVENT_Pos          1
N#define TIMER_STATUS_CNT_ARR_EVENT              ((uint32_t)0x00000002)
N
N#define TIMER_STATUS_ETR_RE_EVENT_Pos           2
N#define TIMER_STATUS_ETR_RE_EVENT               ((uint32_t)0x00000004)
N
N#define TIMER_STATUS_ETR_FE_EVENT_Pos           3
N#define TIMER_STATUS_ETR_FE_EVENT               ((uint32_t)0x00000008)
N
N#define TIMER_STATUS_BRK_EVENT_Pos              4
N#define TIMER_STATUS_BRK_EVENT                  ((uint32_t)0x00000010)
N
N#define TIMER_STATUS_CCR_CAP_EVENT_Pos          5
N#define TIMER_STATUS_CCR_CAP_EVENT_Msk          ((uint32_t)0x000001E0)
N
N#define TIMER_STATUS_CCR_REF_EVENT_Pos          9
N#define TIMER_STATUS_CCR_REF_EVENT_Msk          ((uint32_t)0x00001E00)
N
N#define TIMER_STATUS_CCR1_CAP_EVENT_Pos         13
N#define TIMER_STATUS_CCR1_CAP_EVENT_Msk         ((uint32_t)0x0001E000)
N
N
N/** @} */ /* End of group Periph_TIMER_TIMER_STATUS_Bits */
N
N/** @} */ /* End of group Periph_TIMER_Defines */
N
N/** @defgroup Periph_TIMER_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_TIMER_TIMER_IE_Bits TIMER_IE
N  * @{
N  */
N
N#define TIMER_IE_CNT_ZERO_EVENT_IE_Pos          0
N#define TIMER_IE_CNT_ZERO_EVENT_IE              ((uint32_t)0x00000001)
N
N#define TIMER_IE_CNT_ARR_EVENT_IE_Pos           1
N#define TIMER_IE_CNT_ARR_EVENT_IE               ((uint32_t)0x00000002)
N
N#define TIMER_IE_ETR_RE_EVENT_IE_Pos            2
N#define TIMER_IE_ETR_RE_EVENT_IE                ((uint32_t)0x00000004)
N
N#define TIMER_IE_ETR_FE_EVENT_IE_Pos            3
N#define TIMER_IE_ETR_FE_EVENT_IE                ((uint32_t)0x00000008)
N
N#define TIMER_IE_BRK_EVENT_IE_Pos               4
N#define TIMER_IE_BRK_EVENT_IE                   ((uint32_t)0x00000010)
N
N#define TIMER_IE_CCR_CAP_EVENT_IE_Pos           5
N#define TIMER_IE_CCR_CAP_EVENT_IE_Msk           ((uint32_t)0x000001E0)
N
N#define TIMER_IE_CCR_REF_EVENT_IE_Pos           9
N#define TIMER_IE_CCR_REF_EVENT_IE_Msk           ((uint32_t)0x00001E00)
N
N
N/** @} */ /* End of group Periph_TIMER_TIMER_IE_Bits */
N
N/** @} */ /* End of group Periph_TIMER_Defines */
N
N/** @defgroup Periph_TIMER_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_TIMER_TIMER_DMA_RE_Bits TIMER_DMA_RE
N  * @{
N  */
N
N#define TIMER_DMA_RE_CNT_ZERO_EVENT_RE_Pos      0
N#define TIMER_DMA_RE_CNT_ZERO_EVENT_RE          ((uint32_t)0x00000001)
N
N#define TIMER_DMA_RE_CNT_ARR_EVENT_RE_Pos       1
N#define TIMER_DMA_RE_CNT_ARR_EVENT_RE           ((uint32_t)0x00000002)
N
N#define TIMER_DMA_RE_ETR_RE_EVENT_RE_Pos        2
N#define TIMER_DMA_RE_ETR_RE_EVENT_RE            ((uint32_t)0x00000004)
N
N#define TIMER_DMA_RE_ETR_FE_EVENT_RE_Pos        3
N#define TIMER_DMA_RE_ETR_FE_EVENT_RE            ((uint32_t)0x00000008)
N
N#define TIMER_DMA_RE_BRK_EVENT_RE_Pos           4
N#define TIMER_DMA_RE_BRK_EVENT_RE               ((uint32_t)0x00000010)
N
N#define TIMER_DMA_RE_CCR_CAP_EVENT_RE_Pos       5
N#define TIMER_DMA_RE_CCR_CAP_EVENT_RE_Msk       ((uint32_t)0x000001E0)
N
N#define TIMER_DMA_RE_CCR_REF_EVENT_RE_Pos       9
N#define TIMER_DMA_RE_CCR_REF_EVENT_RE_Msk       ((uint32_t)0x00001E00)
N
N
N/** @} */ /* End of group Periph_TIMER_TIMER_DMA_RE_Bits */
N
N/** @} */ /* End of group Periph_TIMER_Defines */
N
N/** @defgroup Periph_TIMER_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_TIMER_TIMER_CH_CNTRL2_Bits TIMER_CH_CNTRL2
N  * @{
N  */
N
N#define TIMER_CH_CNTRL2_CHSEL1_Pos              0
N#define TIMER_CH_CNTRL2_CHSEL1_Msk              ((uint32_t)0x00000003)
N
N#define TIMER_CH_CNTRL2_CCR1_EN_Pos             2
N#define TIMER_CH_CNTRL2_CCR1_EN                 ((uint32_t)0x00000004)
N
N#define TIMER_CH_CNTRL2_CCRRLD_Pos              3
N#define TIMER_CH_CNTRL2_CCRRLD                  ((uint32_t)0x00000008)
N
N
N/** @} */ /* End of group Periph_TIMER_TIMER_CH_CNTRL2_Bits */
N
N/** @} */ /* End of group Periph_TIMER_Defines */
N
N/** @} */ /* End of group Periph_TIMER */
N
N/** @} */ /* End of group __1901BC1F_Peripheral_Units */
N
N/** @} */ /* End of group __CMSIS */
N
N#endif /* __1901BC1F_TIMER_DEFS_H */
N
N/******************* (C) COPYRIGHT 2010 Phyton *********************************
N*
N* END OF FILE 1901BC1F_timer_defs.h */
L 105 ".\inc\1901BC1F.h" 2
N#include "1901BC1F_adc_defs.h"
L 1 ".\inc\1901BC1F_adc_defs.h" 1
N/**
N  ******************************************************************************
N  * @file    1901BC1F_adc_defs.h
N  * @author  Phyton Application Team
N  * @version V1.0.0
N  * @date    14/01/2011
N  * @brief   This file contains all the Special Function Registers definitions
N  *          for the ADC peripheral unit used in the Milandr 1901BC1F
N  *          microcontrollers.
N  ******************************************************************************
N  * @copy
N  *
N  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
N  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
N  * TIME. AS A RESULT, PHYTON SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
N  * OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
N  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
N  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
N  *
N  * <h2><center>&copy; COPYRIGHT 2010 Phyton</center></h2>
N  ******************************************************************************
N  * FILE 1901BC1F_adc_defs.h
N  */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __1901BC1F_ADC_DEFS_H
N#define __1901BC1F_ADC_DEFS_H
N
N/** @addtogroup __CMSIS CMSIS
N  * @{
N  */
N
N/** @addtogroup __1901BC1F_Peripheral_Units 1901BC1F Peripheral Units
N  * @{
N  */
N
N/** @defgroup Periph_ADC ADC
N  * @{
N  */
N
N/** @defgroup Periph_ADC_Data_Structures Data Structures
N  * @{
N  */
N
N/** @defgroup Periph_ADC_TypeDef ADC_TypeDef
N  * @{
N  */
N
Ntypedef struct
N{
N  __IO uint32_t ADC1_CFG;
X  volatile uint32_t ADC1_CFG;
N  __IO uint32_t ADC2_CFG;
X  volatile uint32_t ADC2_CFG;
N  __IO uint32_t ADC1_H_LEVEL;
X  volatile uint32_t ADC1_H_LEVEL;
N  __IO uint32_t ADC2_H_LEVEL;
X  volatile uint32_t ADC2_H_LEVEL;
N  __IO uint32_t ADC1_L_LEVEL;
X  volatile uint32_t ADC1_L_LEVEL;
N  __IO uint32_t ADC2_L_LEVEL;
X  volatile uint32_t ADC2_L_LEVEL;
N  __IO uint32_t ADC1_RESULT;
X  volatile uint32_t ADC1_RESULT;
N  __IO uint32_t ADC2_RESULT;
X  volatile uint32_t ADC2_RESULT;
N  __IO uint32_t ADC1_STATUS;
X  volatile uint32_t ADC1_STATUS;
N  __IO uint32_t ADC2_STATUS;
X  volatile uint32_t ADC2_STATUS;
N  __IO uint32_t ADC1_CHSEL;
X  volatile uint32_t ADC1_CHSEL;
N  __IO uint32_t ADC2_CHSEL;
X  volatile uint32_t ADC2_CHSEL;
N}ADC_TypeDef;
N
N/** @} */ /* End of group Periph_ADC_TypeDef */
N
N/** @} */ /* End of group Periph_ADC_Data_Structures */
N
N/** @defgroup Periph_ADC_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_ADC_ADC1_CFG_Bits ADC1_CFG
N  * @{
N  */
N
N#define ADC1_CFG_Cfg_REG_ADON_Pos               0
N#define ADC1_CFG_Cfg_REG_ADON                   ((uint32_t)0x00000001)
N
N#define ADC1_CFG_Cfg_REG_GO_Pos                 1
N#define ADC1_CFG_Cfg_REG_GO                     ((uint32_t)0x00000002)
N
N#define ADC1_CFG_Cfg_REG_CLKS_Pos               2
N#define ADC1_CFG_Cfg_REG_CLKS                   ((uint32_t)0x00000004)
N
N#define ADC1_CFG_Cfg_REG_SAMPLE_Pos             3
N#define ADC1_CFG_Cfg_REG_SAMPLE                 ((uint32_t)0x00000008)
N
N#define ADC1_CFG_Cfg_REG_CHS_Pos                4
N#define ADC1_CFG_Cfg_REG_CHS_Msk                ((uint32_t)0x000001F0)
N
N#define ADC1_CFG_Cfg_REG_CHCH_Pos               9
N#define ADC1_CFG_Cfg_REG_CHCH                   ((uint32_t)0x00000200)
N
N#define ADC1_CFG_Cfg_REG_RNGC_Pos               10
N#define ADC1_CFG_Cfg_REG_RNGC                   ((uint32_t)0x00000400)
N
N#define ADC1_CFG_Cfg_M_REF_Pos                  11
N#define ADC1_CFG_Cfg_M_REF                      ((uint32_t)0x00000800)
N
N#define ADC1_CFG_Cfg_REG_DIVCLK_Pos             12
N#define ADC1_CFG_Cfg_REG_DIVCLK_Msk             ((uint32_t)0x0000F000)
N
N#define ADC1_CFG_Cfg_Sync_Conver_Pos            16
N#define ADC1_CFG_Cfg_Sync_Conver                ((uint32_t)0x00010000)
N
N#define ADC1_CFG_TS_EN_Pos                      17
N#define ADC1_CFG_TS_EN                          ((uint32_t)0x00020000)
N
N#define ADC1_CFG_TS_BUF_EN_Pos                  18
N#define ADC1_CFG_TS_BUF_EN                      ((uint32_t)0x00040000)
N
N#define ADC1_CFG_SEL_TS_Pos                     19
N#define ADC1_CFG_SEL_TS                         ((uint32_t)0x00080000)
N
N#define ADC1_CFG_SEL_VREF_Pos                   20
N#define ADC1_CFG_SEL_VREF                       ((uint32_t)0x00100000)
N
N#define ADC1_CFG_TR_Pos                         21
N#define ADC1_CFG_TR_Msk                         ((uint32_t)0x01E00000)
N
N#define ADC1_CFG_Delay_Go_Pos                   25
N#define ADC1_CFG_Delay_Go_Msk                   ((uint32_t)0x0E000000)
N
N#define ADC1_CFG_Delay_ADC_Pos                  28
N#define ADC1_CFG_Delay_ADC_Msk                  ((uint32_t)0xF0000000)
N
N
N/** @} */ /* End of group Periph_ADC_ADC1_CFG_Bits */
N
N/** @} */ /* End of group Periph_ADC_Defines */
N
N/** @defgroup Periph_ADC_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_ADC_ADC2_CFG_Bits ADC2_CFG
N  * @{
N  */
N
N#define ADC2_CFG_Cfg_REG_ADON_Pos               0
N#define ADC2_CFG_Cfg_REG_ADON                   ((uint32_t)0x00000001)
N
N#define ADC2_CFG_Cfg_REG_GO_Pos                 1
N#define ADC2_CFG_Cfg_REG_GO                     ((uint32_t)0x00000002)
N
N#define ADC2_CFG_Cfg_REG_CLKS_Pos               2
N#define ADC2_CFG_Cfg_REG_CLKS                   ((uint32_t)0x00000004)
N
N#define ADC2_CFG_Cfg_REG_SAMPLE_Pos             3
N#define ADC2_CFG_Cfg_REG_SAMPLE                 ((uint32_t)0x00000008)
N
N#define ADC2_CFG_Cfg_REG_CHS_Pos                4
N#define ADC2_CFG_Cfg_REG_CHS_Msk                ((uint32_t)0x000001F0)
N
N#define ADC2_CFG_Cfg_REG_CHCH_Pos               9
N#define ADC2_CFG_Cfg_REG_CHCH                   ((uint32_t)0x00000200)
N
N#define ADC2_CFG_Cfg_REG_RNGC_Pos               10
N#define ADC2_CFG_Cfg_REG_RNGC                   ((uint32_t)0x00000400)
N
N#define ADC2_CFG_Cfg_M_REF_Pos                  11
N#define ADC2_CFG_Cfg_M_REF                      ((uint32_t)0x00000800)
N
N#define ADC2_CFG_Cfg_REG_DIVCLK_Pos             12
N#define ADC2_CFG_Cfg_REG_DIVCLK_Msk             ((uint32_t)0x0000F000)
N
N#define ADC2_CFG_ADC1_OP_Pos                    17
N#define ADC2_CFG_ADC1_OP                        ((uint32_t)0x00020000)
N
N#define ADC2_CFG_ADC2_OP_Pos                    18
N#define ADC2_CFG_ADC2_OP                        ((uint32_t)0x00040000)
N
N#define ADC2_CFG_Delay_Go_Pos                   25
N#define ADC2_CFG_Delay_Go_Msk                   ((uint32_t)0x0E000000)
N
N
N/** @} */ /* End of group Periph_ADC_ADC2_CFG_Bits */
N
N/** @} */ /* End of group Periph_ADC_Defines */
N
N/** @defgroup Periph_ADC_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_ADC_ADC1_RESULT_Bits ADC1_RESULT
N  * @{
N  */
N
N#define ADC1_RESULT_Pos                         0
N#define ADC1_RESULT_Msk                         ((uint32_t)0x00000FFF)
N
N#define ADC1_RESULT_CHANNEL_Pos                 16
N#define ADC1_RESULT_CHANNEL_Msk                 ((uint32_t)0x0FFF0000)
N
N
N/** @} */ /* End of group Periph_ADC_ADC1_RESULT_Bits */
N
N/** @} */ /* End of group Periph_ADC_Defines */
N
N/** @defgroup Periph_ADC_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_ADC_ADC2_RESULT_Bits ADC2_RESULT
N  * @{
N  */
N
N#define ADC2_RESULT_Pos                         0
N#define ADC2_RESULT_Msk                         ((uint32_t)0x00000FFF)
N
N#define ADC2_RESULT_CHANNEL_Pos                 16
N#define ADC2_RESULT_CHANNEL_Msk                 ((uint32_t)0x0FFF0000)
N
N
N/** @} */ /* End of group Periph_ADC_ADC2_RESULT_Bits */
N
N/** @} */ /* End of group Periph_ADC_Defines */
N
N/** @defgroup Periph_ADC_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_ADC_ADC1_STATUS_Bits ADC1_STATUS
N  * @{
N  */
N
N#define ADC1_STATUS_Flg_REG_OVERWRITE_Pos       0
N#define ADC1_STATUS_Flg_REG_OVERWRITE           ((uint32_t)0x00000001)
N
N#define ADC1_STATUS_Flg_REG_AWOIFEN_Pos         1
N#define ADC1_STATUS_Flg_REG_AWOIFEN             ((uint32_t)0x00000002)
N
N#define ADC1_STATUS_Flg_REG_EOCIF_Pos           2
N#define ADC1_STATUS_Flg_REG_EOCIF               ((uint32_t)0x00000004)
N
N#define ADC1_STATUS_AWOIF_IE_Pos                3
N#define ADC1_STATUS_AWOIF_IE                    ((uint32_t)0x00000008)
N
N#define ADC1_STATUS_ECOIF_IE_Pos                4
N#define ADC1_STATUS_ECOIF_IE                    ((uint32_t)0x00000010)
N
N
N/** @} */ /* End of group Periph_ADC_ADC1_STATUS_Bits */
N
N/** @} */ /* End of group Periph_ADC_Defines */
N
N/** @defgroup Periph_ADC_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_ADC_ADC2_STATUS_Bits ADC2_STATUS
N  * @{
N  */
N
N#define ADC2_STATUS_Flg_REG_OVERWRITE_Pos       0
N#define ADC2_STATUS_Flg_REG_OVERWRITE           ((uint32_t)0x00000001)
N
N#define ADC2_STATUS_Flg_REG_AWOIFEN_Pos         1
N#define ADC2_STATUS_Flg_REG_AWOIFEN             ((uint32_t)0x00000002)
N
N#define ADC2_STATUS_Flg_REG_EOCIF_Pos           2
N#define ADC2_STATUS_Flg_REG_EOCIF               ((uint32_t)0x00000004)
N
N#define ADC2_STATUS_AWOIF_IE_Pos                3
N#define ADC2_STATUS_AWOIF_IE                    ((uint32_t)0x00000008)
N
N#define ADC2_STATUS_ECOIF_IE_Pos                4
N#define ADC2_STATUS_ECOIF_IE                    ((uint32_t)0x00000010)
N
N
N/** @} */ /* End of group Periph_ADC_ADC2_STATUS_Bits */
N
N/** @} */ /* End of group Periph_ADC_Defines */
N
N/** @} */ /* End of group Periph_ADC */
N
N/** @} */ /* End of group __1901BC1F_Peripheral_Units */
N
N/** @} */ /* End of group __CMSIS */
N
N#endif /* __1901BC1F_ADC_DEFS_H */
N
N/******************* (C) COPYRIGHT 2010 Phyton *********************************
N*
N* END OF FILE 1901BC1F_adc_defs.h */
L 106 ".\inc\1901BC1F.h" 2
N#include "1901BC1F_dac_defs.h"
L 1 ".\inc\1901BC1F_dac_defs.h" 1
N/**
N  ******************************************************************************
N  * @file    1901BC1F_dac_defs.h
N  * @author  Phyton Application Team
N  * @version V1.0.0
N  * @date    14/01/2011
N  * @brief   This file contains all the Special Function Registers definitions
N  *          for the DAC peripheral unit used in the Milandr 1901BC1F
N  *          microcontrollers.
N  ******************************************************************************
N  * @copy
N  *
N  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
N  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
N  * TIME. AS A RESULT, PHYTON SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
N  * OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
N  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
N  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
N  *
N  * <h2><center>&copy; COPYRIGHT 2010 Phyton</center></h2>
N  ******************************************************************************
N  * FILE 1901BC1F_dac_defs.h
N  */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __1901BC1F_DAC_DEFS_H
N#define __1901BC1F_DAC_DEFS_H
N
N/** @addtogroup __CMSIS CMSIS
N  * @{
N  */
N
N/** @addtogroup __1901BC1F_Peripheral_Units 1901BC1F Peripheral Units
N  * @{
N  */
N
N/** @defgroup Periph_DAC DAC
N  * @{
N  */
N
N/** @defgroup Periph_DAC_Data_Structures Data Structures
N  * @{
N  */
N
N/** @defgroup Periph_DAC_TypeDef DAC_TypeDef
N  * @{
N  */
N
Ntypedef struct
N{
N  __IO uint32_t CFG;
X  volatile uint32_t CFG;
N  __IO uint32_t DAC1_DATA;
X  volatile uint32_t DAC1_DATA;
N  __IO uint32_t DAC2_DATA;
X  volatile uint32_t DAC2_DATA;
N}DAC_TypeDef;
N
N/** @} */ /* End of group Periph_DAC_TypeDef */
N
N/** @} */ /* End of group Periph_DAC_Data_Structures */
N
N/** @defgroup Periph_DAC_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_DAC_DAC_CFG_Bits DAC_CFG
N  * @{
N  */
N
N#define DAC_CFG_Cfg_M_REF0_Pos                  0
N#define DAC_CFG_Cfg_M_REF0                      ((uint32_t)0x00000001)
N
N#define DAC_CFG_Cfg_M_REF1_Pos                  1
N#define DAC_CFG_Cfg_M_REF1                      ((uint32_t)0x00000002)
N
N#define DAC_CFG_Cfg_ON_DAC0_Pos                 2
N#define DAC_CFG_Cfg_ON_DAC0                     ((uint32_t)0x00000004)
N
N#define DAC_CFG_Cfg_ON_DAC1_Pos                 3
N#define DAC_CFG_Cfg_ON_DAC1                     ((uint32_t)0x00000008)
N
N#define DAC_CFG_Cfg_SYNC_A_Pos                  4
N#define DAC_CFG_Cfg_SYNC_A                      ((uint32_t)0x00000010)
N
N
N/** @} */ /* End of group Periph_DAC_DAC_CFG_Bits */
N
N/** @} */ /* End of group Periph_DAC_Defines */
N
N/** @defgroup Periph_DAC_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_DAC_DAC1_DATA_Bits DAC1_DATA
N  * @{
N  */
N
N#define DAC1_DATA_DAC0DATA_Pos                  0
N#define DAC1_DATA_DAC0DATA_Msk                  ((uint32_t)0x00000FFF)
N
N#define DAC1_DATA_DAC1DATA_Pos                  16
N#define DAC1_DATA_DAC1DATA_Msk                  ((uint32_t)0x0FFF0000)
N
N
N/** @} */ /* End of group Periph_DAC_DAC1_DATA_Bits */
N
N/** @} */ /* End of group Periph_DAC_Defines */
N
N/** @defgroup Periph_DAC_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_DAC_DAC2_DATA_Bits DAC2_DATA
N  * @{
N  */
N
N#define DAC2_DATA_DAC1DATA_Pos                  0
N#define DAC2_DATA_DAC1DATA_Msk                  ((uint32_t)0x00000FFF)
N
N#define DAC2_DATA_DAC0DATA_Pos                  16
N#define DAC2_DATA_DAC0DATA_Msk                  ((uint32_t)0x0FFF0000)
N
N
N/** @} */ /* End of group Periph_DAC_DAC2_DATA_Bits */
N
N/** @} */ /* End of group Periph_DAC_Defines */
N
N/** @} */ /* End of group Periph_DAC */
N
N/** @} */ /* End of group __1901BC1F_Peripheral_Units */
N
N/** @} */ /* End of group __CMSIS */
N
N#endif /* __1901BC1F_DAC_DEFS_H */
N
N/******************* (C) COPYRIGHT 2010 Phyton *********************************
N*
N* END OF FILE 1901BC1F_dac_defs.h */
L 107 ".\inc\1901BC1F.h" 2
N#include "1901BC1F_comp_defs.h"
L 1 ".\inc\1901BC1F_comp_defs.h" 1
N/**
N  ******************************************************************************
N  * @file    1901BC1F_comp_defs.h
N  * @author  Phyton Application Team
N  * @version V1.0.0
N  * @date    14/01/2011
N  * @brief   This file contains all the Special Function Registers definitions
N  *          for the COMP peripheral unit used in the Milandr 1901BC1F
N  *          microcontrollers.
N  ******************************************************************************
N  * @copy
N  *
N  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
N  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
N  * TIME. AS A RESULT, PHYTON SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
N  * OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
N  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
N  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
N  *
N  * <h2><center>&copy; COPYRIGHT 2010 Phyton</center></h2>
N  ******************************************************************************
N  * FILE 1901BC1F_comp_defs.h
N  */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __1901BC1F_COMP_DEFS_H
N#define __1901BC1F_COMP_DEFS_H
N
N/** @addtogroup __CMSIS CMSIS
N  * @{
N  */
N
N/** @addtogroup __1901BC1F_Peripheral_Units 1901BC1F Peripheral Units
N  * @{
N  */
N
N/** @defgroup Periph_COMP COMP
N  * @{
N  */
N
N/** @defgroup Periph_COMP_Data_Structures Data Structures
N  * @{
N  */
N
N/** @defgroup Periph_COMP_TypeDef COMP_TypeDef
N  * @{
N  */
N
Ntypedef struct
N{
N  __IO uint32_t CFG;
X  volatile uint32_t CFG;
N  __IO uint32_t RESULT;
X  volatile uint32_t RESULT;
N  __IO uint32_t RESULT_LATCH;
X  volatile uint32_t RESULT_LATCH;
N}COMP_TypeDef;
N
N/** @} */ /* End of group Periph_COMP_TypeDef */
N
N/** @} */ /* End of group Periph_COMP_Data_Structures */
N
N/** @defgroup Periph_COMP_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_COMP_COMP_CFG_Bits COMP_CFG
N  * @{
N  */
N
N#define COMP_CFG_ON_Pos                         0
N#define COMP_CFG_ON                             ((uint32_t)0x00000001)
N
N#define COMP_CFG_CVRR_Pos                       1
N#define COMP_CFG_CVRR                           ((uint32_t)0x00000002)
N
N#define COMP_CFG_CVRSS_Pos                      2
N#define COMP_CFG_CVRSS                          ((uint32_t)0x00000004)
N
N#define COMP_CFG_CVREN_Pos                      3
N#define COMP_CFG_CVREN                          ((uint32_t)0x00000008)
N
N#define COMP_CFG_CVR_Pos                        4
N#define COMP_CFG_CVR_Msk                        ((uint32_t)0x000000F0)
N
N#define COMP_CFG_CREF_Pos                       8
N#define COMP_CFG_CREF                           ((uint32_t)0x00000100)
N
N#define COMP_CFG_CCH_Pos                        9
N#define COMP_CFG_CCH_Msk                        ((uint32_t)0x00000600)
N
N#define COMP_CFG_INV_Pos                        11
N#define COMP_CFG_INV                            ((uint32_t)0x00000800)
N
N#define COMP_CFG_Ready_Pos                      12
N#define COMP_CFG_Ready                          ((uint32_t)0x00001000)
N
N#define COMP_CFG_CMPIE_Pos                      13
N#define COMP_CFG_CMPIE                          ((uint32_t)0x00002000)
N
N
N/** @} */ /* End of group Periph_COMP_COMP_CFG_Bits */
N
N/** @} */ /* End of group Periph_COMP_Defines */
N
N/** @defgroup Periph_COMP_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_COMP_COMP_RESULT_Bits COMP_RESULT
N  * @{
N  */
N
N#define COMP_RESULT_Rslt_Sy_Pos                 0
N#define COMP_RESULT_Rslt_Sy                     ((uint32_t)0x00000001)
N
N#define COMP_RESULT_Rslt_As_Pos                 1
N#define COMP_RESULT_Rslt_As                     ((uint32_t)0x00000002)
N
N#define COMP_RESULT_Rst_lch_Pos                 2
N#define COMP_RESULT_Rst_lch                     ((uint32_t)0x00000004)
N
N
N/** @} */ /* End of group Periph_COMP_COMP_RESULT_Bits */
N
N/** @} */ /* End of group Periph_COMP_Defines */
N
N/** @} */ /* End of group Periph_COMP */
N
N/** @} */ /* End of group __1901BC1F_Peripheral_Units */
N
N/** @} */ /* End of group __CMSIS */
N
N#endif /* __1901BC1F_COMP_DEFS_H */
N
N/******************* (C) COPYRIGHT 2010 Phyton *********************************
N*
N* END OF FILE 1901BC1F_comp_defs.h */
L 108 ".\inc\1901BC1F.h" 2
N#include "1901BC1F_port_defs.h"
L 1 ".\inc\1901BC1F_port_defs.h" 1
N/**
N  ******************************************************************************
N  * @file    1901BC1F_port_defs.h
N  * @author  Phyton Application Team
N  * @version V1.0.0
N  * @date    14/01/2011
N  * @brief   This file contains all the Special Function Registers definitions
N  *          for the PORT peripheral unit used in the Milandr 1901BC1F
N  *          microcontrollers.
N  ******************************************************************************
N  * @copy
N  *
N  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
N  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
N  * TIME. AS A RESULT, PHYTON SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
N  * OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
N  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
N  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
N  *
N  * <h2><center>&copy; COPYRIGHT 2010 Phyton</center></h2>
N  ******************************************************************************
N  * FILE 1901BC1F_port_defs.h
N  */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __1901BC1F_PORT_DEFS_H
N#define __1901BC1F_PORT_DEFS_H
N
N/** @addtogroup __CMSIS CMSIS
N  * @{
N  */
N
N/** @addtogroup __1901BC1F_Peripheral_Units 1901BC1F Peripheral Units
N  * @{
N  */
N
N/** @defgroup Periph_PORT PORT
N  * @{
N  */
N
N/** @defgroup Periph_PORT_Data_Structures Data Structures
N  * @{
N  */
N
N/** @defgroup Periph_PORT_TypeDef PORT_TypeDef
N  * @{
N  */
N
Ntypedef struct
N{
N  __IO uint32_t RXTX;
X  volatile uint32_t RXTX;
N  __IO uint32_t OE;
X  volatile uint32_t OE;
N  __IO uint32_t FUNC;
X  volatile uint32_t FUNC;
N  __IO uint32_t ANALOG;
X  volatile uint32_t ANALOG;
N  __IO uint32_t PULL;
X  volatile uint32_t PULL;
N  __IO uint32_t PD;
X  volatile uint32_t PD;
N  __IO uint32_t PWR;
X  volatile uint32_t PWR;
N  __IO uint32_t GFEN;
X  volatile uint32_t GFEN;
N  __IO uint32_t PORTx_SET;
X  volatile uint32_t PORTx_SET;
N  __IO uint32_t PORTx_CLR;
X  volatile uint32_t PORTx_CLR;
N  __IO uint32_t PORTx_RD;
X  volatile uint32_t PORTx_RD;
N
N}PORT_TypeDef;
N
N/** @} */ /* End of group Periph_PORT_TypeDef */
N
N/** @} */ /* End of group Periph_PORT_Data_Structures */
N
N/** @defgroup Periph_PORT_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_PORT_PORT_FUNC_Bits PORT_FUNC
N  * @{
N  */
N
N#define PORT_FUNC_MODE0_Pos                     0
N#define PORT_FUNC_MODE0_Msk                     ((uint32_t)0x00000003)
N
N#define PORT_FUNC_MODE1_Pos                     2
N#define PORT_FUNC_MODE1_Msk                     ((uint32_t)0x0000000C)
N
N#define PORT_FUNC_MODE2_Pos                     4
N#define PORT_FUNC_MODE2_Msk                     ((uint32_t)0x00000030)
N
N#define PORT_FUNC_MODE3_Pos                     6
N#define PORT_FUNC_MODE3_Msk                     ((uint32_t)0x000000C0)
N
N#define PORT_FUNC_MODE4_Pos                     8
N#define PORT_FUNC_MODE4_Msk                     ((uint32_t)0x00000300)
N
N#define PORT_FUNC_MODE5_Pos                     10
N#define PORT_FUNC_MODE5_Msk                     ((uint32_t)0x00000C00)
N
N#define PORT_FUNC_MODE6_Pos                     12
N#define PORT_FUNC_MODE6_Msk                     ((uint32_t)0x00003000)
N
N#define PORT_FUNC_MODE7_Pos                     14
N#define PORT_FUNC_MODE7_Msk                     ((uint32_t)0x0000C000)
N
N#define PORT_FUNC_MODE8_Pos                     16
N#define PORT_FUNC_MODE8_Msk                     ((uint32_t)0x00030000)
N
N#define PORT_FUNC_MODE9_Pos                     18
N#define PORT_FUNC_MODE9_Msk                     ((uint32_t)0x000C0000)
N
N#define PORT_FUNC_MODE10_Pos                    20
N#define PORT_FUNC_MODE10_Msk                    ((uint32_t)0x00300000)
N
N#define PORT_FUNC_MODE11_Pos                    22
N#define PORT_FUNC_MODE11_Msk                    ((uint32_t)0x00C00000)
N
N#define PORT_FUNC_MODE12_Pos                    24
N#define PORT_FUNC_MODE12_Msk                    ((uint32_t)0x03000000)
N
N#define PORT_FUNC_MODE13_Pos                    26
N#define PORT_FUNC_MODE13_Msk                    ((uint32_t)0x0C000000)
N
N#define PORT_FUNC_MODE14_Pos                    28
N#define PORT_FUNC_MODE14_Msk                    ((uint32_t)0x30000000)
N
N#define PORT_FUNC_MODE15_Pos                    30
N#define PORT_FUNC_MODE15_Msk                    ((uint32_t)0xC0000000)
N
N
N/** @} */ /* End of group Periph_PORT_PORT_FUNC_Bits */
N
N/** @} */ /* End of group Periph_PORT_Defines */
N
N/** @defgroup Periph_PORT_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_PORT_PORT_PWR_Bits PORT_PWR
N  * @{
N  */
N
N#define PORT_PWR_PWR0_Pos                       0
N#define PORT_PWR_PWR0_Msk                       ((uint32_t)0x00000003)
N
N#define PORT_PWR_PWR1_Pos                       2
N#define PORT_PWR_PWR1_Msk                       ((uint32_t)0x0000000C)
N
N#define PORT_PWR_PWR2_Pos                       4
N#define PORT_PWR_PWR2_Msk                       ((uint32_t)0x00000030)
N
N#define PORT_PWR_PWR3_Pos                       6
N#define PORT_PWR_PWR3_Msk                       ((uint32_t)0x000000C0)
N
N#define PORT_PWR_PWR4_Pos                       8
N#define PORT_PWR_PWR4_Msk                       ((uint32_t)0x00000300)
N
N#define PORT_PWR_PWR5_Pos                       10
N#define PORT_PWR_PWR5_Msk                       ((uint32_t)0x00000C00)
N
N#define PORT_PWR_PWR6_Pos                       12
N#define PORT_PWR_PWR6_Msk                       ((uint32_t)0x00003000)
N
N#define PORT_PWR_PWR7_Pos                       14
N#define PORT_PWR_PWR7_Msk                       ((uint32_t)0x0000C000)
N
N#define PORT_PWR_PWR8_Pos                       16
N#define PORT_PWR_PWR8_Msk                       ((uint32_t)0x00030000)
N
N#define PORT_PWR_PWR9_Pos                       18
N#define PORT_PWR_PWR9_Msk                       ((uint32_t)0x000C0000)
N
N#define PORT_PWR_PWR10_Pos                      20
N#define PORT_PWR_PWR10_Msk                      ((uint32_t)0x00300000)
N
N#define PORT_PWR_PWR11_Pos                      22
N#define PORT_PWR_PWR11_Msk                      ((uint32_t)0x00C00000)
N
N#define PORT_PWR_PWR12_Pos                      24
N#define PORT_PWR_PWR12_Msk                      ((uint32_t)0x03000000)
N
N#define PORT_PWR_PWR13_Pos                      26
N#define PORT_PWR_PWR13_Msk                      ((uint32_t)0x0C000000)
N
N#define PORT_PWR_PWR14_Pos                      28
N#define PORT_PWR_PWR14_Msk                      ((uint32_t)0x30000000)
N
N#define PORT_PWR_PWR15_Pos                      30
N#define PORT_PWR_PWR15_Msk                      ((uint32_t)0xC0000000)
N
N
N/** @} */ /* End of group Periph_PORT_PORT_PWR_Bits */
N
N/** @} */ /* End of group Periph_PORT_Defines */
N
N/** @} */ /* End of group Periph_PORT */
N
N/** @} */ /* End of group __1901BC1F_Peripheral_Units */
N
N/** @} */ /* End of group __CMSIS */
N
N#endif /* __1901BC1F_PORT_DEFS_H */
N
N/******************* (C) COPYRIGHT 2010 Phyton *********************************
N*
N* END OF FILE 1901BC1F_port_defs.h */
N
L 109 ".\inc\1901BC1F.h" 2
N#include "1901BC1F_bkp_defs.h"
L 1 ".\inc\1901BC1F_bkp_defs.h" 1
N/**
N  ******************************************************************************
N  * @file    1901BC1F_bkp_defs.h
N  * @author  Phyton Application Team
N  * @version V1.0.0
N  * @date    14/01/2011
N  * @brief   This file contains all the Special Function Registers definitions
N  *          for the BKP peripheral unit used in the Milandr 1901BC1F
N  *          microcontrollers.
N  ******************************************************************************
N  * @copy
N  *
N  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
N  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
N  * TIME. AS A RESULT, PHYTON SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
N  * OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
N  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
N  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
N  *
N  * <h2><center>&copy; COPYRIGHT 2010 Phyton</center></h2>
N  ******************************************************************************
N  * FILE 1901BC1F_bkp_defs.h
N  */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __1901BC1F_BKP_DEFS_H
N#define __1901BC1F_BKP_DEFS_H
N
N/** @addtogroup __CMSIS CMSIS
N  * @{
N  */
N
N/** @addtogroup __1901BC1F_Peripheral_Units 1901BC1F Peripheral Units
N  * @{
N  */
N
N/** @defgroup Periph_BKP BKP
N  * @{
N  */
N
N/** @defgroup Periph_BKP_Data_Structures Data Structures
N  * @{
N  */
N
N/** @defgroup Periph_BKP_TypeDef BKP_TypeDef
N  * @{
N  */
N
Ntypedef struct
N{
N  __IO uint32_t REG_00;
X  volatile uint32_t REG_00;
N  __IO uint32_t REG_01;
X  volatile uint32_t REG_01;
N  __IO uint32_t REG_02;
X  volatile uint32_t REG_02;
N  __IO uint32_t REG_03;
X  volatile uint32_t REG_03;
N  __IO uint32_t REG_04;
X  volatile uint32_t REG_04;
N  __IO uint32_t REG_05;
X  volatile uint32_t REG_05;
N  __IO uint32_t REG_06;
X  volatile uint32_t REG_06;
N  __IO uint32_t REG_07;
X  volatile uint32_t REG_07;
N  __IO uint32_t REG_08;
X  volatile uint32_t REG_08;
N  __IO uint32_t REG_09;
X  volatile uint32_t REG_09;
N  __IO uint32_t REG_0A;
X  volatile uint32_t REG_0A;
N  __IO uint32_t REG_0B;
X  volatile uint32_t REG_0B;
N  __IO uint32_t REG_0C;
X  volatile uint32_t REG_0C;
N  __IO uint32_t REG_0D;
X  volatile uint32_t REG_0D;
N  __IO uint32_t REG_0E;
X  volatile uint32_t REG_0E;
N  __IO uint32_t REG_0F;
X  volatile uint32_t REG_0F;
N  __IO uint32_t RTC_CNT;
X  volatile uint32_t RTC_CNT;
N  __IO uint32_t RTC_DIV;
X  volatile uint32_t RTC_DIV;
N  __IO uint32_t RTC_PRL;
X  volatile uint32_t RTC_PRL;
N  __IO uint32_t RTC_ALRM;
X  volatile uint32_t RTC_ALRM;
N  __IO uint32_t RTC_CS;
X  volatile uint32_t RTC_CS;
N}BKP_TypeDef;
N
N/** @} */ /* End of group Periph_BKP_TypeDef */
N
N/** @} */ /* End of group Periph_BKP_Data_Structures */
N
N/** @defgroup Periph_BKP_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_BKP_BKP_REG_0E_Bits BKP_REG_0E
N  * @{
N  */
N
N#define BKP_REG_0E_LOW_Pos                      0
N#define BKP_REG_0E_LOW_Msk                      ((uint32_t)0x00000007)
N
N#define BKP_REG_0E_SelectRI_Pos                 3
N#define BKP_REG_0E_SelectRI_Msk                 ((uint32_t)0x00000038)
N
N#define BKP_REG_0E_JTAGA_Pos                    6
N#define BKP_REG_0E_JTAGA                        ((uint32_t)0x00000040)
N
N#define BKP_REG_0E_JTAGB_Pos                    7
N#define BKP_REG_0E_JTAGB                        ((uint32_t)0x00000080)
N
N#define BKP_REG_0E_Trim_Pos                     8
N#define BKP_REG_0E_Trim_Msk                     ((uint32_t)0x00000700)
N
N#define BKP_REG_0E_FPOR_Pos                     11
N#define BKP_REG_0E_FPOR                         ((uint32_t)0x00000800)
N
N#define BKP_REG_0E_BKP_REG_Pos                  12
N#define BKP_REG_0E_BKP_REG_Msk                  ((uint32_t)0xFFFFF000)
N
N
N/** @} */ /* End of group Periph_BKP_BKP_REG_0E_Bits */
N
N/** @} */ /* End of group Periph_BKP_Defines */
N
N/** @defgroup Periph_BKP_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_BKP_BKP_REG_0F_Bits BKP_REG_0F
N  * @{
N  */
N
N#define BKP_REG_0F_LSE_ON_Pos                   0
N#define BKP_REG_0F_LSE_ON                       ((uint32_t)0x00000001)
N
N#define BKP_REG_0F_LSE_BYP_Pos                  1
N#define BKP_REG_0F_LSE_BYP                      ((uint32_t)0x00000002)
N
N#define BKP_REG_0F_RTC_SEL_Pos                  2
N#define BKP_REG_0F_RTC_SEL_Msk                  ((uint32_t)0x0000000C)
N
N#define BKP_REG_0F_RTC_EN_Pos                   4
N#define BKP_REG_0F_RTC_EN                       ((uint32_t)0x00000010)
N
N#define BKP_REG_0F_CAL_Pos                      5
N#define BKP_REG_0F_CAL_Msk                      ((uint32_t)0x00001FE0)
N
N#define BKP_REG_0F_LSE_RDY_Pos                  13
N#define BKP_REG_0F_LSE_RDY                      ((uint32_t)0x00002000)
N
N#define BKP_REG_0F_BKP_REG_Pos                  14
N#define BKP_REG_0F_BKP_REG                      ((uint32_t)0x00004000)
N
N#define BKP_REG_0F_LSI_ON_Pos                   15
N#define BKP_REG_0F_LSI_ON                       ((uint32_t)0x00008000)
N
N#define BKP_REG_0F_LSI_TRIM_Pos                 16
N#define BKP_REG_0F_LSI_TRIM_Msk                 ((uint32_t)0x001F0000)
N
N#define BKP_REG_0F_LSI_RDY_Pos                  21
N#define BKP_REG_0F_LSI_RDY                      ((uint32_t)0x00200000)
N
N#define BKP_REG_0F_HSI_ON_Pos                   22
N#define BKP_REG_0F_HSI_ON                       ((uint32_t)0x00400000)
N
N#define BKP_REG_0F_HSI_RDY_Pos                  23
N#define BKP_REG_0F_HSI_RDY                      ((uint32_t)0x00800000)
N
N#define BKP_REG_0F_HSI_TRIM_Pos                 24
N#define BKP_REG_0F_HSI_TRIM_Msk                 ((uint32_t)0x3F000000)
N
N#define BKP_REG_0F_STANDBY_Pos                  30
N#define BKP_REG_0F_STANDBY                      ((uint32_t)0x40000000)
N
N#define BKP_REG_0F_RTC_RESET_Pos                31
N#define BKP_REG_0F_RTC_RESET                    ((uint32_t)0x80000000)
N
N
N/** @} */ /* End of group Periph_BKP_BKP_REG_0F_Bits */
N
N/** @} */ /* End of group Periph_BKP_Defines */
N
N/** @defgroup Periph_BKP_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_BKP_BKP_RTC_CS_Bits BKP_RTC_CS
N  * @{
N  */
N
N#define BKP_RTC_CS_OWF_Pos                      0
N#define BKP_RTC_CS_OWF                          ((uint32_t)0x00000001)
N
N#define BKP_RTC_CS_SECF_Pos                     1
N#define BKP_RTC_CS_SECF                         ((uint32_t)0x00000002)
N
N#define BKP_RTC_CS_ALRF_Pos                     2
N#define BKP_RTC_CS_ALRF                         ((uint32_t)0x00000004)
N
N#define BKP_RTC_CS_OWF_IE_Pos                   3
N#define BKP_RTC_CS_OWF_IE                       ((uint32_t)0x00000008)
N
N#define BKP_RTC_CS_SECF_IE_Pos                  4
N#define BKP_RTC_CS_SECF_IE                      ((uint32_t)0x00000010)
N
N#define BKP_RTC_CS_ALRF_IE_Pos                  5
N#define BKP_RTC_CS_ALRF_IE                      ((uint32_t)0x00000020)
N
N#define BKP_RTC_CS_WEC_Pos                      6
N#define BKP_RTC_CS_WEC                          ((uint32_t)0x00000040)
N
N
N/** @} */ /* End of group Periph_BKP_BKP_RTC_CS_Bits */
N
N/** @} */ /* End of group Periph_BKP_Defines */
N
N/** @} */ /* End of group Periph_BKP */
N
N/** @} */ /* End of group __1901BC1F_Peripheral_Units */
N
N/** @} */ /* End of group __CMSIS */
N
N#endif /* __1901BC1F_BKP_DEFS_H */
N
N/******************* (C) COPYRIGHT 2010 Phyton *********************************
N*
N* END OF FILE 1901BC1F_bkp_defs.h */
L 110 ".\inc\1901BC1F.h" 2
N#include "1901BC1F_ext_bus_cntrl_defs.h"
L 1 ".\inc\1901BC1F_ext_bus_cntrl_defs.h" 1
N/**
N  ******************************************************************************
N  * @file    1901BC1F_ext_bus_cntrl_defs.h
N  * @author  Phyton Application Team
N  * @version V1.0.0
N  * @date    14/01/2011
N  * @brief   This file contains all the Special Function Registers definitions
N  *          for the EXT_BUS_CNTRL peripheral unit used in the Milandr 1901BC1F
N  *          microcontrollers.
N  ******************************************************************************
N  * @copy
N  *
N  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
N  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
N  * TIME. AS A RESULT, PHYTON SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
N  * OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
N  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
N  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
N  *
N  * <h2><center>&copy; COPYRIGHT 2010 Phyton</center></h2>
N  ******************************************************************************
N  * FILE 1901BC1F_ext_bus_cntrl_defs.h
N  */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __1901BC1F_EXT_BUS_CNTRL_DEFS_H
N#define __1901BC1F_EXT_BUS_CNTRL_DEFS_H
N
N/** @addtogroup __CMSIS CMSIS
N  * @{
N  */
N
N/** @addtogroup __1901BC1F_Peripheral_Units 1901BC1F Peripheral Units
N  * @{
N  */
N
N/** @defgroup Periph_EXT_BUS_CNTRL EXT_BUS_CNTRL
N  * @{
N  */
N
N/** @defgroup Periph_EXT_BUS_CNTRL_Data_Structures Data Structures
N  * @{
N  */
N
N/** @defgroup Periph_EXT_BUS_CNTRL_TypeDef EXT_BUS_CNTRL_TypeDef
N  * @{
N  */
N
Ntypedef struct
N{
N       uint32_t RESERVED0[20];
N  __IO uint32_t NAND_CYCLES;
X  volatile uint32_t NAND_CYCLES;
N  __IO uint32_t EXT_BUS_CONTROL;
X  volatile uint32_t EXT_BUS_CONTROL;
N}EXT_BUS_CNTRL_TypeDef;
N
N/** @} */ /* End of group Periph_EXT_BUS_CNTRL_TypeDef */
N
N/** @} */ /* End of group Periph_EXT_BUS_CNTRL_Data_Structures */
N
N/** @defgroup Periph_EXT_BUS_CNTRL_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_EXT_BUS_CNTRL_EXT_BUS_CNTRL_NAND_CYCLES_Bits EXT_BUS_CNTRL_NAND_CYCLES
N  * @{
N  */
N
N#define EXT_BUS_CNTRL_NAND_CYCLES_t_rc_Pos      0
N#define EXT_BUS_CNTRL_NAND_CYCLES_t_rc_Msk      ((uint32_t)0x0000000F)
N
N#define EXT_BUS_CNTRL_NAND_CYCLES_t_wc_Pos      4
N#define EXT_BUS_CNTRL_NAND_CYCLES_t_wc_Msk      ((uint32_t)0x000000F0)
N
N#define EXT_BUS_CNTRL_NAND_CYCLES_t_rea_Pos     8
N#define EXT_BUS_CNTRL_NAND_CYCLES_t_rea_Msk     ((uint32_t)0x00000F00)
N
N#define EXT_BUS_CNTRL_NAND_CYCLES_t_wp_Pos      12
N#define EXT_BUS_CNTRL_NAND_CYCLES_t_wp_Msk      ((uint32_t)0x0000F000)
N
N#define EXT_BUS_CNTRL_NAND_CYCLES_t_whr_Pos     16
N#define EXT_BUS_CNTRL_NAND_CYCLES_t_whr_Msk     ((uint32_t)0x000F0000)
N
N#define EXT_BUS_CNTRL_NAND_CYCLES_t_alea_Pos    20
N#define EXT_BUS_CNTRL_NAND_CYCLES_t_alea_Msk    ((uint32_t)0x00F00000)
N
N#define EXT_BUS_CNTRL_NAND_CYCLES_t_rr_Pos      24
N#define EXT_BUS_CNTRL_NAND_CYCLES_t_rr_Msk      ((uint32_t)0x0F000000)
N
N
N/** @} */ /* End of group Periph_EXT_BUS_CNTRL_EXT_BUS_CNTRL_NAND_CYCLES_Bits */
N
N/** @} */ /* End of group Periph_EXT_BUS_CNTRL_Defines */
N
N/** @defgroup Periph_EXT_BUS_CNTRL_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_EXT_BUS_CNTRL_EXT_BUS_CNTRL_EXT_BUS_CONTROL_Bits EXT_BUS_CNTRL_EXT_BUS_CONTROL
N  * @{
N  */
N
N#define EXT_BUS_CNTRL_EXT_BUS_CONTROL_ROM_Pos   0
N#define EXT_BUS_CNTRL_EXT_BUS_CONTROL_ROM       ((uint32_t)0x00000001)
N
N#define EXT_BUS_CNTRL_EXT_BUS_CONTROL_RAM_Pos   1
N#define EXT_BUS_CNTRL_EXT_BUS_CONTROL_RAM       ((uint32_t)0x00000002)
N
N#define EXT_BUS_CNTRL_EXT_BUS_CONTROL_NAND_Pos  2
N#define EXT_BUS_CNTRL_EXT_BUS_CONTROL_NAND      ((uint32_t)0x00000004)
N
N#define EXT_BUS_CNTRL_EXT_BUS_CONTROL_CPOL_Pos  3
N#define EXT_BUS_CNTRL_EXT_BUS_CONTROL_CPOL      ((uint32_t)0x00000008)
N
N#define EXT_BUS_CNTRL_EXT_BUS_CONTROL_BUSY_Pos  7
N#define EXT_BUS_CNTRL_EXT_BUS_CONTROL_BUSY      ((uint32_t)0x00000080)
N
N#define EXT_BUS_CNTRL_EXT_BUS_CONTROL_WAIT_STATE_Pos 12
N#define EXT_BUS_CNTRL_EXT_BUS_CONTROL_WAIT_STATE_Msk ((uint32_t)0x0000F000)
N
N
N/** @} */ /* End of group Periph_EXT_BUS_CNTRL_EXT_BUS_CNTRL_EXT_BUS_CONTROL_Bits */
N
N/** @} */ /* End of group Periph_EXT_BUS_CNTRL_Defines */
N
N/** @} */ /* End of group Periph_EXT_BUS_CNTRL */
N
N/** @} */ /* End of group __1901BC1F_Peripheral_Units */
N
N/** @} */ /* End of group __CMSIS */
N
N#endif /* __1901BC1F_EXT_BUS_CNTRL_DEFS_H */
N
N/******************* (C) COPYRIGHT 2010 Phyton *********************************
N*
N* END OF FILE 1901BC1F_ext_bus_cntrl_defs.h */
L 111 ".\inc\1901BC1F.h" 2
N#include "1901BC1F_dsp_bsp_defs.h"
L 1 ".\inc\1901BC1F_dsp_bsp_defs.h" 1
N/**
N  ******************************************************************************
N  * @file    1901BC1F_dsp_bsp_defs.h
N  * @author  Phyton Application Team
N  * @version V1.0.0
N  * @date    14/01/2011
N  * @brief   This file contains all the Special Function Registers definitions
N  *          for the DSP_BSP peripheral unit used in the Milandr 1901BC1F
N  *          microcontrollers.
N  ******************************************************************************
N  * @copy
N  *
N  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
N  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
N  * TIME. AS A RESULT, PHYTON SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
N  * OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
N  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
N  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
N  *
N  * <h2><center>&copy; COPYRIGHT 2010 Phyton</center></h2>
N  ******************************************************************************
N  * FILE 1901BC1F_dsp_bsp_defs.h
N  */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __1901BC1F_DSP_BSP_DEFS_H
N#define __1901BC1F_DSP_BSP_DEFS_H
N
N/** @addtogroup __CMSIS CMSIS
N  * @{
N  */
N
N/** @addtogroup __1901BC1F_Peripheral_Units 1901BC1F Peripheral Units
N  * @{
N  */
N
N/** @defgroup Periph_DSP_BSP DSP_BSP
N  * @{
N  */
N
N/** @defgroup Periph_DSP_BSP_Data_Structures Data Structures
N  * @{
N  */
N
N/** @defgroup Periph_DSP_BSP_TypeDef DSP_BSP_TypeDef
N  * @{
N  */
N
Ntypedef struct
N{
N  __IO uint32_t DDR;
X  volatile uint32_t DDR;
N  __IO uint32_t DXR;
X  volatile uint32_t DXR;
N  __IO uint32_t SPSA;
X  volatile uint32_t SPSA;
N  __IO uint32_t CtrlD;
X  volatile uint32_t CtrlD;
N}DSP_BSP_TypeDef;
N
N/** @} */ /* End of group Periph_DSP_BSP_TypeDef */
N
N/** @} */ /* End of group Periph_DSP_BSP_Data_Structures */
N
N/** @} */ /* End of group Periph_DSP_BSP */
N
N/** @} */ /* End of group __1901BC1F_Peripheral_Units */
N
N/** @} */ /* End of group __CMSIS */
N
N#endif /* __1901BC1F_DSP_BSP_DEFS_H */
N
N/******************* (C) COPYRIGHT 2010 Phyton *********************************
N*
N* END OF FILE 1901BC1F_dsp_bsp_defs.h */
L 112 ".\inc\1901BC1F.h" 2
N#include "1901BC1F_dsp_tim_defs.h"
L 1 ".\inc\1901BC1F_dsp_tim_defs.h" 1
N/**
N  ******************************************************************************
N  * @file    1901BC1F_dsp_tim_defs.h
N  * @author  Phyton Application Team
N  * @version V1.0.0
N  * @date    14/01/2011
N  * @brief   This file contains all the Special Function Registers definitions
N  *          for the DSP_TIM peripheral unit used in the Milandr 1901BC1F
N  *          microcontrollers.
N  ******************************************************************************
N  * @copy
N  *
N  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
N  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
N  * TIME. AS A RESULT, PHYTON SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
N  * OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
N  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
N  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
N  *
N  * <h2><center>&copy; COPYRIGHT 2010 Phyton</center></h2>
N  ******************************************************************************
N  * FILE 1901BC1F_dsp_tim_defs.h
N  */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __1901BC1F_DSP_TIM_DEFS_H
N#define __1901BC1F_DSP_TIM_DEFS_H
N
N/** @addtogroup __CMSIS CMSIS
N  * @{
N  */
N
N/** @addtogroup __1901BC1F_Peripheral_Units 1901BC1F Peripheral Units
N  * @{
N  */
N
N/** @defgroup Periph_DSP_TIM DSP_TIM
N  * @{
N  */
N
N/** @defgroup Periph_DSP_TIM_Data_Structures Data Structures
N  * @{
N  */
N
N/** @defgroup Periph_DSP_TIM_TypeDef DSP_TIM_TypeDef
N  * @{
N  */
N
Ntypedef struct
N{
N  __IO uint32_t TIM_PRD;
X  volatile uint32_t TIM_PRD;
N  __IO uint32_t TCR;
X  volatile uint32_t TCR;
N}DSP_TIM_TypeDef;
N
N/** @} */ /* End of group Periph_DSP_TIM_TypeDef */
N
N/** @} */ /* End of group Periph_DSP_TIM_Data_Structures */
N
N/** @defgroup Periph_DSP_TIM_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_DSP_TIM_DSP_TIM_TCR_Bits DSP_TIM_TCR
N  * @{
N  */
N
N#define DSP_TIM_TCR_TDDR0_Pos                   0
N#define DSP_TIM_TCR_TDDR0                       ((uint32_t)0x00000001)
N
N#define DSP_TIM_TCR_TDDR1_Pos                   1
N#define DSP_TIM_TCR_TDDR1                       ((uint32_t)0x00000002)
N
N#define DSP_TIM_TCR_TDDR2_Pos                   2
N#define DSP_TIM_TCR_TDDR2                       ((uint32_t)0x00000004)
N
N#define DSP_TIM_TCR_TDDR3_Pos                   3
N#define DSP_TIM_TCR_TDDR3                       ((uint32_t)0x00000008)
N
N#define DSP_TIM_TCR_TSS_Pos                     4
N#define DSP_TIM_TCR_TSS                         ((uint32_t)0x00000010)
N
N#define DSP_TIM_TCR_TRB_Pos                     5
N#define DSP_TIM_TCR_TRB                         ((uint32_t)0x00000020)
N
N#define DSP_TIM_TCR_PSC0_Pos                    6
N#define DSP_TIM_TCR_PSC0                        ((uint32_t)0x00000040)
N
N#define DSP_TIM_TCR_PSC1_Pos                    7
N#define DSP_TIM_TCR_PSC1                        ((uint32_t)0x00000080)
N
N#define DSP_TIM_TCR_PSC2_Pos                    8
N#define DSP_TIM_TCR_PSC2                        ((uint32_t)0x00000100)
N
N#define DSP_TIM_TCR_PSC3_Pos                    9
N#define DSP_TIM_TCR_PSC3                        ((uint32_t)0x00000200)
N
N#define DSP_TIM_TCR_FREE_Pos                    10
N#define DSP_TIM_TCR_FREE                        ((uint32_t)0x00000400)
N
N#define DSP_TIM_TCR_SOFT_Pos                    11
N#define DSP_TIM_TCR_SOFT                        ((uint32_t)0x00000800)
N
N
N/** @} */ /* End of group Periph_DSP_TIM_DSP_TIM_TCR_Bits */
N
N/** @} */ /* End of group Periph_DSP_TIM_Defines */
N
N/** @} */ /* End of group Periph_DSP_TIM */
N
N/** @} */ /* End of group __1901BC1F_Peripheral_Units */
N
N/** @} */ /* End of group __CMSIS */
N
N#endif /* __1901BC1F_DSP_TIM_DEFS_H */
N
N/******************* (C) COPYRIGHT 2010 Phyton *********************************
N*
N* END OF FILE 1901BC1F_dsp_tim_defs.h */
L 113 ".\inc\1901BC1F.h" 2
N#include "1901BC1F_dsp_irq_defs.h"
L 1 ".\inc\1901BC1F_dsp_irq_defs.h" 1
N/**
N  ******************************************************************************
N  * @file    1901BC1F_dsp_irq_defs.h
N  * @author  Phyton Application Team
N  * @version V1.0.0
N  * @date    14/01/2011
N  * @brief   This file contains all the Special Function Registers definitions
N  *          for the DSP_IRQ peripheral unit used in the Milandr 1901BC1F
N  *          microcontrollers.
N  ******************************************************************************
N  * @copy
N  *
N  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
N  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
N  * TIME. AS A RESULT, PHYTON SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
N  * OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
N  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
N  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
N  *
N  * <h2><center>&copy; COPYRIGHT 2010 Phyton</center></h2>
N  ******************************************************************************
N  * FILE 1901BC1F_dsp_irq_defs.h
N  */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __1901BC1F_DSP_IRQ_DEFS_H
N#define __1901BC1F_DSP_IRQ_DEFS_H
N
N/** @addtogroup __CMSIS CMSIS
N  * @{
N  */
N
N/** @addtogroup __1901BC1F_Peripheral_Units 1901BC1F Peripheral Units
N  * @{
N  */
N
N/** @defgroup Periph_DSP_IRQ DSP_IRQ
N  * @{
N  */
N
N/** @defgroup Periph_DSP_IRQ_Data_Structures Data Structures
N  * @{
N  */
N
N/** @defgroup Periph_DSP_IRQ_TypeDef DSP_IRQ_TypeDef
N  * @{
N  */
N
Ntypedef struct
N{
N  __IO uint32_t IRQ;
X  volatile uint32_t IRQ;
N}DSP_IRQ_TypeDef;
N
N/** @} */ /* End of group Periph_DSP_IRQ_TypeDef */
N
N/** @} */ /* End of group Periph_DSP_IRQ_Data_Structures */
N
N/** @defgroup Periph_DSP_IRQ_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_DSP_IRQ_DSP_IRQ_Bits DSP_IRQ
N  * @{
N  */
N
N#define DSP_IRQ_DIRQ0_Pos                       0
N#define DSP_IRQ_DIRQ0                           ((uint32_t)0x00000001)
N
N#define DSP_IRQ_DIRQ1_Pos                       1
N#define DSP_IRQ_DIRQ1                           ((uint32_t)0x00000002)
N
N#define DSP_IRQ_DIRQ2_Pos                       2
N#define DSP_IRQ_DIRQ2                           ((uint32_t)0x00000004)
N
N#define DSP_IRQ_DIRQ3_Pos                       3
N#define DSP_IRQ_DIRQ3                           ((uint32_t)0x00000008)
N
N#define DSP_IRQ_TIRQ_Pos                        4
N#define DSP_IRQ_TIRQ                            ((uint32_t)0x00000010)
N
N#define DSP_IRQ_RIRQ1_Pos                       5
N#define DSP_IRQ_RIRQ1                           ((uint32_t)0x00000020)
N
N#define DSP_IRQ_XIRQ1_Pos                       6
N#define DSP_IRQ_XIRQ1                           ((uint32_t)0x00000040)
N
N#define DSP_IRQ_RIRQ2_Pos                       7
N#define DSP_IRQ_RIRQ2                           ((uint32_t)0x00000080)
N
N#define DSP_IRQ_XIRQ2_Pos                       8
N#define DSP_IRQ_XIRQ2                           ((uint32_t)0x00000100)
N
N#define DSP_IRQ_RIRQ3_Pos                       9
N#define DSP_IRQ_RIRQ3                           ((uint32_t)0x00000200)
N
N#define DSP_IRQ_XIRQ3_Pos                       10
N#define DSP_IRQ_XIRQ3                           ((uint32_t)0x00000400)
N
N#define DSP_IRQ_CDIRQ_Pos                       11
N#define DSP_IRQ_CDIRQ                           ((uint32_t)0x00000800)
N
N#define DSP_IRQ_CRIRQ_Pos                       12
N#define DSP_IRQ_CRIRQ                           ((uint32_t)0x00001000)
N
N#define DSP_IRQ_DSNR_Pos                        15
N#define DSP_IRQ_DSNR                            ((uint32_t)0x00008000)
N
N#define DSP_IRQ_AIRQ0_Pos                       16
N#define DSP_IRQ_AIRQ0                           ((uint32_t)0x00010000)
N
N#define DSP_IRQ_AIRQ1_Pos                       17
N#define DSP_IRQ_AIRQ1                           ((uint32_t)0x00020000)
N
N#define DSP_IRQ_AIRQ2_Pos                       18
N#define DSP_IRQ_AIRQ2                           ((uint32_t)0x00040000)
N
N#define DSP_IRQ_AIRQ3_Pos                       19
N#define DSP_IRQ_AIRQ3                           ((uint32_t)0x00080000)
N
N#define DSP_IRQ_ANMI_Pos                        20
N#define DSP_IRQ_ANMI                            ((uint32_t)0x00100000)
N
N#define DSP_IRQ_ASNR_Pos                        31
N#define DSP_IRQ_ASNR                            ((uint32_t)0x80000000)
N
N
N/** @} */ /* End of group Periph_DSP_IRQ_DSP_IRQ_Bits */
N
N/** @} */ /* End of group Periph_DSP_IRQ_Defines */
N
N/** @} */ /* End of group Periph_DSP_IRQ */
N
N/** @} */ /* End of group __1901BC1F_Peripheral_Units */
N
N/** @} */ /* End of group __CMSIS */
N
N#endif /* __1901BC1F_DSP_IRQ_DEFS_H */
N
N/******************* (C) COPYRIGHT 2010 Phyton *********************************
N*
N* END OF FILE 1901BC1F_dsp_irq_defs.h */
L 114 ".\inc\1901BC1F.h" 2
N#include "1901BC1F_dsp_crpt_defs.h"
L 1 ".\inc\1901BC1F_dsp_crpt_defs.h" 1
N/**
N  ******************************************************************************
N  * @file    1901BC1F_dsp_crpt_defs.h
N  * @author  Phyton Application Team
N  * @version V1.0.0
N  * @date    14/01/2011
N  * @brief   This file contains all the Special Function Registers definitions
N  *          for the DSP_CRPT peripheral unit used in the Milandr 1901BC1F
N  *          microcontrollers.
N  ******************************************************************************
N  * @copy
N  *
N  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
N  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
N  * TIME. AS A RESULT, PHYTON SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
N  * OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
N  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
N  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
N  *
N  * <h2><center>&copy; COPYRIGHT 2010 Phyton</center></h2>
N  ******************************************************************************
N  * FILE 1901BC1F_dsp_crpt_defs.h
N  */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __1901BC1F_DSP_CRPT_DEFS_H
N#define __1901BC1F_DSP_CRPT_DEFS_H
N
N/** @addtogroup __CMSIS CMSIS
N  * @{
N  */
N
N/** @addtogroup __1901BC1F_Peripheral_Units 1901BC1F Peripheral Units
N  * @{
N  */
N
N/** @defgroup Periph_DSP_CRPT DSP_CRPT
N  * @{
N  */
N
N/** @defgroup Periph_DSP_CRPT_Data_Structures Data Structures
N  * @{
N  */
N
N/** @defgroup Periph_DSP_CRPT_TypeDef DSP_CRPT_TypeDef
N  * @{
N  */
N
Ntypedef struct
N{
N  __IO uint32_t CWR;
X  volatile uint32_t CWR;
N  __IO uint32_t SR;
X  volatile uint32_t SR;
N  __IO uint32_t DATA;
X  volatile uint32_t DATA;
N  __IO uint32_t KR;
X  volatile uint32_t KR;
N  __IO uint32_t SYNR;
X  volatile uint32_t SYNR;
N  __IO uint32_t CR;
X  volatile uint32_t CR;
N  __IO uint32_t IMIT;
X  volatile uint32_t IMIT;
N  __IO uint32_t ITER;
X  volatile uint32_t ITER;
N}DSP_CRPT_TypeDef;
N
N/** @} */ /* End of group Periph_DSP_CRPT_TypeDef */
N
N/** @} */ /* End of group Periph_DSP_CRPT_Data_Structures */
N
N/** @defgroup Periph_DSP_CRPT_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_DSP_CRPT_DSP_CRPT_CWR_Bits DSP_CRPT_CWR
N  * @{
N  */
N
N#define DSP_CRPT_CWR_MODE0_CRPT_Pos             0
N#define DSP_CRPT_CWR_MODE0_CRPT                 ((uint32_t)0x00000001)
N
N#define DSP_CRPT_CWR_MODE1_CRPT_Pos             1
N#define DSP_CRPT_CWR_MODE1_CRPT                 ((uint32_t)0x00000002)
N
N#define DSP_CRPT_CWR_IM_Pos                     2
N#define DSP_CRPT_CWR_IM                         ((uint32_t)0x00000004)
N
N#define DSP_CRPT_CWR_START_Pos                  3
N#define DSP_CRPT_CWR_START                      ((uint32_t)0x00000008)
N
N#define DSP_CRPT_CWR_DIR_Pos                    4
N#define DSP_CRPT_CWR_DIR                        ((uint32_t)0x00000010)
N
N#define DSP_CRPT_CWR_IE_CRPT_Pos                5
N#define DSP_CRPT_CWR_IE_CRPT                    ((uint32_t)0x00000020)
N
N#define DSP_CRPT_CWR_RST_Pos                    6
N#define DSP_CRPT_CWR_RST                        ((uint32_t)0x00000040)
N
N#define DSP_CRPT_CWR_BIST_Pos                   7
N#define DSP_CRPT_CWR_BIST                       ((uint32_t)0x00000080)
N
N
N/** @} */ /* End of group Periph_DSP_CRPT_DSP_CRPT_CWR_Bits */
N
N/** @} */ /* End of group Periph_DSP_CRPT_Defines */
N
N/** @defgroup Periph_DSP_CRPT_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_DSP_CRPT_DSP_CRPT_SR_Bits DSP_CRPT_SR
N  * @{
N  */
N
N#define DSP_CRPT_SR_READY_CRPT_Pos              0
N#define DSP_CRPT_SR_READY_CRPT                  ((uint32_t)0x00000001)
N
N#define DSP_CRPT_SR_ERROR_CRPT_Pos              1
N#define DSP_CRPT_SR_ERROR_CRPT                  ((uint32_t)0x00000002)
N
N#define DSP_CRPT_SR_KF_Pos                      2
N#define DSP_CRPT_SR_KF                          ((uint32_t)0x00000004)
N
N#define DSP_CRPT_SR_DW_Pos                      3
N#define DSP_CRPT_SR_DW                          ((uint32_t)0x00000008)
N
N#define DSP_CRPT_SR_DR_Pos                      4
N#define DSP_CRPT_SR_DR                          ((uint32_t)0x00000010)
N
N#define DSP_CRPT_SR_SW_Pos                      5
N#define DSP_CRPT_SR_SW                          ((uint32_t)0x00000020)
N
N#define DSP_CRPT_SR_KW_Pos                      6
N#define DSP_CRPT_SR_KW                          ((uint32_t)0x00000040)
N
N#define DSP_CRPT_SR_DNC_BIST_Pos                7
N#define DSP_CRPT_SR_DNC_BIST                    ((uint32_t)0x00000080)
N
N
N/** @} */ /* End of group Periph_DSP_CRPT_DSP_CRPT_SR_Bits */
N
N/** @} */ /* End of group Periph_DSP_CRPT_Defines */
N
N/** @defgroup Periph_DSP_CRPT_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_DSP_CRPT_DSP_CRPT_ITER_Bits DSP_CRPT_ITER
N  * @{
N  */
N
N#define DSP_CRPT_ITER_ITER0_Pos                 0
N#define DSP_CRPT_ITER_ITER0                     ((uint32_t)0x00000001)
N
N#define DSP_CRPT_ITER_ITER1_Pos                 1
N#define DSP_CRPT_ITER_ITER1                     ((uint32_t)0x00000002)
N
N#define DSP_CRPT_ITER_ITER2_Pos                 2
N#define DSP_CRPT_ITER_ITER2                     ((uint32_t)0x00000004)
N
N#define DSP_CRPT_ITER_ITER3_Pos                 3
N#define DSP_CRPT_ITER_ITER3                     ((uint32_t)0x00000008)
N
N#define DSP_CRPT_ITER_ITER4_Pos                 4
N#define DSP_CRPT_ITER_ITER4                     ((uint32_t)0x00000010)
N
N#define DSP_CRPT_ITER_ITER5_Pos                 5
N#define DSP_CRPT_ITER_ITER5                     ((uint32_t)0x00000020)
N
N#define DSP_CRPT_ITER_EN_CRPT_Pos               6
N#define DSP_CRPT_ITER_EN_CRPT                   ((uint32_t)0x00000040)
N
N
N/** @} */ /* End of group Periph_DSP_CRPT_DSP_CRPT_ITER_Bits */
N
N/** @} */ /* End of group Periph_DSP_CRPT_Defines */
N
N/** @} */ /* End of group Periph_DSP_CRPT */
N
N/** @} */ /* End of group __1901BC1F_Peripheral_Units */
N
N/** @} */ /* End of group __CMSIS */
N
N#endif /* __1901BC1F_DSP_CRPT_DEFS_H */
N
N/******************* (C) COPYRIGHT 2010 Phyton *********************************
N*
N* END OF FILE 1901BC1F_dsp_crpt_defs.h */
L 115 ".\inc\1901BC1F.h" 2
N#include "1901BC1F_dsp_acd_defs.h"
L 1 ".\inc\1901BC1F_dsp_acd_defs.h" 1
N/**
N  ******************************************************************************
N  * @file    1901BC1F_dsp_acd_defs.h
N  * @author  Phyton Application Team
N  * @version V1.0.0
N  * @date    14/01/2011
N  * @brief   This file contains all the Special Function Registers definitions
N  *          for the DSP_ACD peripheral unit used in the Milandr 1901BC1F
N  *          microcontrollers.
N  ******************************************************************************
N  * @copy
N  *
N  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
N  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
N  * TIME. AS A RESULT, PHYTON SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
N  * OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
N  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
N  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
N  *
N  * <h2><center>&copy; COPYRIGHT 2010 Phyton</center></h2>
N  ******************************************************************************
N  * FILE 1901BC1F_dsp_acd_defs.h
N  */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __1901BC1F_DSP_ACD_DEFS_H
N#define __1901BC1F_DSP_ACD_DEFS_H
N
N/** @addtogroup __CMSIS CMSIS
N  * @{
N  */
N
N/** @addtogroup __1901BC1F_Peripheral_Units 1901BC1F Peripheral Units
N  * @{
N  */
N
N/** @defgroup Periph_DSP_ACD DSP_ACD
N  * @{
N  */
N
N/** @defgroup Periph_DSP_ACD_Data_Structures Data Structures
N  * @{
N  */
N
N/** @defgroup Periph_DSP_ACD_TypeDef DSP_ACD_TypeDef
N  * @{
N  */
N
Ntypedef struct
N{
N  __IO uint32_t POWCTL;
X  volatile uint32_t POWCTL;
N  __IO uint32_t ADCCTL;
X  volatile uint32_t ADCCTL;
N  __IO uint32_t DACCTL;
X  volatile uint32_t DACCTL;
N  __IO uint32_t MASKCTL;
X  volatile uint32_t MASKCTL;
N  __IO uint32_t IRQFLAG;
X  volatile uint32_t IRQFLAG;
N  __IO uint32_t ADCREG;
X  volatile uint32_t ADCREG;
N  __IO uint32_t DACREG;
X  volatile uint32_t DACREG;
N}DSP_ACD_TypeDef;
N
N/** @} */ /* End of group Periph_DSP_ACD_TypeDef */
N
N/** @} */ /* End of group Periph_DSP_ACD_Data_Structures */
N
N/** @defgroup Periph_DSP_ACD_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_DSP_ACD_DSP_ACD_POWCTL_Bits DSP_ACD_POWCTL
N  * @{
N  */
N
N#define DSP_ACD_POWCTL_ADCEN_Pos                0
N#define DSP_ACD_POWCTL_ADCEN                    ((uint32_t)0x00000001)
N
N#define DSP_ACD_POWCTL_DACEN_Pos                1
N#define DSP_ACD_POWCTL_DACEN                    ((uint32_t)0x00000002)
N
N#define DSP_ACD_POWCTL_IIREN_Pos                2
N#define DSP_ACD_POWCTL_IIREN                    ((uint32_t)0x00000004)
N
N
N/** @} */ /* End of group Periph_DSP_ACD_DSP_ACD_POWCTL_Bits */
N
N/** @} */ /* End of group Periph_DSP_ACD_Defines */
N
N/** @defgroup Periph_DSP_ACD_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_DSP_ACD_DSP_ACD_ADCCTL_Bits DSP_ACD_ADCCTL
N  * @{
N  */
N
N#define DSP_ACD_ADCCTL_ADGGAIN0_Pos             0
N#define DSP_ACD_ADCCTL_ADGGAIN0                 ((uint32_t)0x00000001)
N
N#define DSP_ACD_ADCCTL_ADGGAIN1_Pos             1
N#define DSP_ACD_ADCCTL_ADGGAIN1                 ((uint32_t)0x00000002)
N
N#define DSP_ACD_ADCCTL_ADGGAIN2_Pos             2
N#define DSP_ACD_ADCCTL_ADGGAIN2                 ((uint32_t)0x00000004)
N
N#define DSP_ACD_ADCCTL_ADGGAIN3_Pos             3
N#define DSP_ACD_ADCCTL_ADGGAIN3                 ((uint32_t)0x00000008)
N
N#define DSP_ACD_ADCCTL_ADGGAIN4_Pos             4
N#define DSP_ACD_ADCCTL_ADGGAIN4                 ((uint32_t)0x00000010)
N
N#define DSP_ACD_ADCCTL_ADGGAIN5_Pos             5
N#define DSP_ACD_ADCCTL_ADGGAIN5                 ((uint32_t)0x00000020)
N
N#define DSP_ACD_ADCCTL_INBG0_Pos                6
N#define DSP_ACD_ADCCTL_INBG0                    ((uint32_t)0x00000040)
N
N#define DSP_ACD_ADCCTL_INBG1_Pos                7
N#define DSP_ACD_ADCCTL_INBG1                    ((uint32_t)0x00000080)
N
N#define DSP_ACD_ADCCTL_AINSEL0_Pos              8
N#define DSP_ACD_ADCCTL_AINSEL0                  ((uint32_t)0x00000100)
N
N#define DSP_ACD_ADCCTL_AINSEL1_Pos              9
N#define DSP_ACD_ADCCTL_AINSEL1                  ((uint32_t)0x00000200)
N
N#define DSP_ACD_ADCCTL_ODADC_Pos                10
N#define DSP_ACD_ADCCTL_ODADC                    ((uint32_t)0x00000400)
N
N#define DSP_ACD_ADCCTL_ICONT_Pos                11
N#define DSP_ACD_ADCCTL_ICONT                    ((uint32_t)0x00000800)
N
N#define DSP_ACD_ADCCTL_ADCRES_Pos               12
N#define DSP_ACD_ADCCTL_ADCRES                   ((uint32_t)0x00001000)
N
N
N/** @} */ /* End of group Periph_DSP_ACD_DSP_ACD_ADCCTL_Bits */
N
N/** @} */ /* End of group Periph_DSP_ACD_Defines */
N
N/** @defgroup Periph_DSP_ACD_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_DSP_ACD_DSP_ACD_DACCTL_Bits DSP_ACD_DACCTL
N  * @{
N  */
N
N#define DSP_ACD_DACCTL_DAGAIN0_Pos              0
N#define DSP_ACD_DACCTL_DAGAIN0                  ((uint32_t)0x00000001)
N
N#define DSP_ACD_DACCTL_DAGGAIN1_Pos             1
N#define DSP_ACD_DACCTL_DAGGAIN1                 ((uint32_t)0x00000002)
N
N#define DSP_ACD_DACCTL_DAGGAIN2_Pos             2
N#define DSP_ACD_DACCTL_DAGGAIN2                 ((uint32_t)0x00000004)
N
N#define DSP_ACD_DACCTL_DAGGAIN3_Pos             3
N#define DSP_ACD_DACCTL_DAGGAIN3                 ((uint32_t)0x00000008)
N
N#define DSP_ACD_DACCTL_DAGGAIN4_Pos             4
N#define DSP_ACD_DACCTL_DAGGAIN4                 ((uint32_t)0x00000010)
N
N#define DSP_ACD_DACCTL_DAGGAIN5_Pos             5
N#define DSP_ACD_DACCTL_DAGGAIN5                 ((uint32_t)0x00000020)
N
N#define DSP_ACD_DACCTL_MUTE1_Pos                6
N#define DSP_ACD_DACCTL_MUTE1                    ((uint32_t)0x00000040)
N
N#define DSP_ACD_DACCTL_ODAMP_Pos                7
N#define DSP_ACD_DACCTL_ODAMP                    ((uint32_t)0x00000080)
N
N#define DSP_ACD_DACCTL_ODBIAS_Pos               8
N#define DSP_ACD_DACCTL_ODBIAS                   ((uint32_t)0x00000100)
N
N#define DSP_ACD_DACCTL_ODDAC_Pos                9
N#define DSP_ACD_DACCTL_ODDAC                    ((uint32_t)0x00000200)
N
N#define DSP_ACD_DACCTL_OVECBF_Pos               10
N#define DSP_ACD_DACCTL_OVECBF                   ((uint32_t)0x00000400)
N
N#define DSP_ACD_DACCTL_OVECBS_Pos               11
N#define DSP_ACD_DACCTL_OVECBS                   ((uint32_t)0x00000800)
N
N#define DSP_ACD_DACCTL_SIDETON0_Pos             12
N#define DSP_ACD_DACCTL_SIDETON0                 ((uint32_t)0x00001000)
N
N#define DSP_ACD_DACCTL_SIDETON1_Pos             13
N#define DSP_ACD_DACCTL_SIDETON1                 ((uint32_t)0x00002000)
N
N#define DSP_ACD_DACCTL_SIDETON2_Pos             14
N#define DSP_ACD_DACCTL_SIDETON2                 ((uint32_t)0x00004000)
N
N#define DSP_ACD_DACCTL_DACRES_Pos               15
N#define DSP_ACD_DACCTL_DACRES                   ((uint32_t)0x00008000)
N
N
N/** @} */ /* End of group Periph_DSP_ACD_DSP_ACD_DACCTL_Bits */
N
N/** @} */ /* End of group Periph_DSP_ACD_Defines */
N
N/** @defgroup Periph_DSP_ACD_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_DSP_ACD_DSP_ACD_MASKCTL_Bits DSP_ACD_MASKCTL
N  * @{
N  */
N
N#define DSP_ACD_MASKCTL_DAOVFM_Pos              0
N#define DSP_ACD_MASKCTL_DAOVFM                  ((uint32_t)0x00000001)
N
N#define DSP_ACD_MASKCTL_ADCVFM_Pos              1
N#define DSP_ACD_MASKCTL_ADCVFM                  ((uint32_t)0x00000002)
N
N#define DSP_ACD_MASKCTL_ADCNSM_Pos              2
N#define DSP_ACD_MASKCTL_ADCNSM                  ((uint32_t)0x00000004)
N
N#define DSP_ACD_MASKCTL_DACNSM_Pos              3
N#define DSP_ACD_MASKCTL_DACNSM                  ((uint32_t)0x00000008)
N
N#define DSP_ACD_MASKCTL_OVERCURM_Pos            4
N#define DSP_ACD_MASKCTL_OVERCURM                ((uint32_t)0x00000010)
N
N
N/** @} */ /* End of group Periph_DSP_ACD_DSP_ACD_MASKCTL_Bits */
N
N/** @} */ /* End of group Periph_DSP_ACD_Defines */
N
N/** @defgroup Periph_DSP_ACD_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_DSP_ACD_DSP_ACD_IRQFLAG_Bits DSP_ACD_IRQFLAG
N  * @{
N  */
N
N#define DSP_ACD_IRQFLAG_DAOVF_Pos               0
N#define DSP_ACD_IRQFLAG_DAOVF                   ((uint32_t)0x00000001)
N
N#define DSP_ACD_IRQFLAG_ADCVF_Pos               1
N#define DSP_ACD_IRQFLAG_ADCVF                   ((uint32_t)0x00000002)
N
N#define DSP_ACD_IRQFLAG_ADCNS_Pos               2
N#define DSP_ACD_IRQFLAG_ADCNS                   ((uint32_t)0x00000004)
N
N#define DSP_ACD_IRQFLAG_DACNS_Pos               3
N#define DSP_ACD_IRQFLAG_DACNS                   ((uint32_t)0x00000008)
N
N#define DSP_ACD_IRQFLAG_OVERCUR_Pos             4
N#define DSP_ACD_IRQFLAG_OVERCUR                 ((uint32_t)0x00000010)
N
N
N/** @} */ /* End of group Periph_DSP_ACD_DSP_ACD_IRQFLAG_Bits */
N
N/** @} */ /* End of group Periph_DSP_ACD_Defines */
N
N/** @} */ /* End of group Periph_DSP_ACD */
N
N/** @} */ /* End of group __1901BC1F_Peripheral_Units */
N
N/** @} */ /* End of group __CMSIS */
N
N#endif /* __1901BC1F_DSP_ACD_DEFS_H */
N
N/******************* (C) COPYRIGHT 2010 Phyton *********************************
N*
N* END OF FILE 1901BC1F_dsp_acd_defs.h */
L 116 ".\inc\1901BC1F.h" 2
N#include "1901BC1F_dsp_clk_defs.h"
L 1 ".\inc\1901BC1F_dsp_clk_defs.h" 1
N/**
N  ******************************************************************************
N  * @file    1901BC1F_dsp_clk_defs.h
N  * @author  Phyton Application Team
N  * @version V1.0.0
N  * @date    14/01/2011
N  * @brief   This file contains all the Special Function Registers definitions
N  *          for the DSP_CLK peripheral unit used in the Milandr 1901BC1F
N  *          microcontrollers.
N  ******************************************************************************
N  * @copy
N  *
N  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
N  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
N  * TIME. AS A RESULT, PHYTON SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
N  * OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
N  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
N  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
N  *
N  * <h2><center>&copy; COPYRIGHT 2010 Phyton</center></h2>
N  ******************************************************************************
N  * FILE 1901BC1F_dsp_clk_defs.h
N  */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __1901BC1F_DSP_CLK_DEFS_H
N#define __1901BC1F_DSP_CLK_DEFS_H
N
N/** @addtogroup __CMSIS CMSIS
N  * @{
N  */
N
N/** @addtogroup __1901BC1F_Peripheral_Units 1901BC1F Peripheral Units
N  * @{
N  */
N
N/** @defgroup Periph_DSP_CLK DSP_CLK
N  * @{
N  */
N
N/** @defgroup Periph_DSP_CLK_Data_Structures Data Structures
N  * @{
N  */
N
N/** @defgroup Periph_DSP_CLK_TypeDef DSP_CLK_TypeDef
N  * @{
N  */
N
Ntypedef struct
N{
N  __IO uint32_t CLKMD;
X  volatile uint32_t CLKMD;
N}DSP_CLK_TypeDef;
N
N/** @} */ /* End of group Periph_DSP_CLK_TypeDef */
N
N/** @} */ /* End of group Periph_DSP_CLK_Data_Structures */
N
N/** @defgroup Periph_DSP_CLK_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_DSP_CLK_DSP_CLK_CLKMD_Bits DSP_CLK_CLKMD
N  * @{
N  */
N
N#define DSP_CLK_CLKMD_CRP_Pos                   0
N#define DSP_CLK_CLKMD_CRP                       ((uint32_t)0x00000001)
N
N#define DSP_CLK_CLKMD_CDC_Pos                   1
N#define DSP_CLK_CLKMD_CDC                       ((uint32_t)0x00000002)
N
N#define DSP_CLK_CLKMD_TMR_Pos                   2
N#define DSP_CLK_CLKMD_TMR                       ((uint32_t)0x00000004)
N
N#define DSP_CLK_CLKMD_DMA_Pos                   3
N#define DSP_CLK_CLKMD_DMA                       ((uint32_t)0x00000008)
N
N#define DSP_CLK_CLKMD_MC3_Pos                   4
N#define DSP_CLK_CLKMD_MC3                       ((uint32_t)0x00000010)
N
N#define DSP_CLK_CLKMD_PC3_Pos                   5
N#define DSP_CLK_CLKMD_PC3                       ((uint32_t)0x00000020)
N
N#define DSP_CLK_CLKMD_MC2_Pos                   6
N#define DSP_CLK_CLKMD_MC2                       ((uint32_t)0x00000040)
N
N#define DSP_CLK_CLKMD_PC2_Pos                   7
N#define DSP_CLK_CLKMD_PC2                       ((uint32_t)0x00000080)
N
N#define DSP_CLK_CLKMD_MC1_Pos                   8
N#define DSP_CLK_CLKMD_MC1                       ((uint32_t)0x00000100)
N
N#define DSP_CLK_CLKMD_PC1_Pos                   9
N#define DSP_CLK_CLKMD_PC1                       ((uint32_t)0x00000200)
N
N#define DSP_CLK_CLKMD_CDM_Pos                   10
N#define DSP_CLK_CLKMD_CDM                       ((uint32_t)0x00000400)
N
N#define DSP_CLK_CLKMD_CPM_Pos                   11
N#define DSP_CLK_CLKMD_CPM                       ((uint32_t)0x00000800)
N
N#define DSP_CLK_CLKMD_CPU_Pos                   12
N#define DSP_CLK_CLKMD_CPU                       ((uint32_t)0x00001000)
N
N
N/** @} */ /* End of group Periph_DSP_CLK_DSP_CLK_CLKMD_Bits */
N
N/** @} */ /* End of group Periph_DSP_CLK_Defines */
N
N/** @} */ /* End of group Periph_DSP_CLK */
N
N/** @} */ /* End of group __1901BC1F_Peripheral_Units */
N
N/** @} */ /* End of group __CMSIS */
N
N#endif /* __1901BC1F_DSP_CLK_DEFS_H */
N
N/******************* (C) COPYRIGHT 2010 Phyton *********************************
N*
N* END OF FILE 1901BC1F_dsp_clk_defs.h */
L 117 ".\inc\1901BC1F.h" 2
N#include "1901BC1F_dsp_dma_defs.h"
L 1 ".\inc\1901BC1F_dsp_dma_defs.h" 1
N/**
N  ******************************************************************************
N  * @file    1901BC1F_dsp_dma_defs.h
N  * @author  Phyton Application Team
N  * @version V1.0.0
N  * @date    14/01/2011
N  * @brief   This file contains all the Special Function Registers definitions
N  *          for the DSP_DMA peripheral unit used in the Milandr 1901BC1F
N  *          microcontrollers.
N  ******************************************************************************
N  * @copy
N  *
N  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
N  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
N  * TIME. AS A RESULT, PHYTON SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
N  * OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
N  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
N  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
N  *
N  * <h2><center>&copy; COPYRIGHT 2010 Phyton</center></h2>
N  ******************************************************************************
N  * FILE 1901BC1F_dsp_dma_defs.h
N  */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __1901BC1F_DSP_DMA_DEFS_H
N#define __1901BC1F_DSP_DMA_DEFS_H
N
N/** @addtogroup __CMSIS CMSIS
N  * @{
N  */
N
N/** @addtogroup __1901BC1F_Peripheral_Units 1901BC1F Peripheral Units
N  * @{
N  */
N
N/** @defgroup Periph_DSP_DMA DSP_DMA
N  * @{
N  */
N
N/** @defgroup Periph_DSP_DMA_Data_Structures Data Structures
N  * @{
N  */
N
N/** @defgroup Periph_DSP_DMA_TypeDef DSP_DMA_TypeDef
N  * @{
N  */
N
Ntypedef struct
N{
N  __IO uint32_t DMA_STATUS;
X  volatile uint32_t DMA_STATUS;
N  __IO uint32_t DMA_CFG;
X  volatile uint32_t DMA_CFG;
N  __IO uint32_t CTRL_BASE_PTR;
X  volatile uint32_t CTRL_BASE_PTR;
N  __IO uint32_t ALT_CTRL_BASE_PTR;
X  volatile uint32_t ALT_CTRL_BASE_PTR;
N  __IO uint32_t DMA_WAITONREQ_STATUS;
X  volatile uint32_t DMA_WAITONREQ_STATUS;
N  __IO uint32_t CHNL_SW_REQUEST;
X  volatile uint32_t CHNL_SW_REQUEST;
N  __IO uint32_t CHNL_USEBURST_SET;
X  volatile uint32_t CHNL_USEBURST_SET;
N  __IO uint32_t CHNL_USEBURST_CLR;
X  volatile uint32_t CHNL_USEBURST_CLR;
N  __IO uint32_t CHNL_REQ_MASK_SET;
X  volatile uint32_t CHNL_REQ_MASK_SET;
N  __IO uint32_t CHNL_REQ_MASK_CLR;
X  volatile uint32_t CHNL_REQ_MASK_CLR;
N  __IO uint32_t CHNL_ENABLE_SET;
X  volatile uint32_t CHNL_ENABLE_SET;
N  __IO uint32_t CHNL_ENABLE_CLR;
X  volatile uint32_t CHNL_ENABLE_CLR;
N  __IO uint32_t CHNL_PRI_ALT_SET;
X  volatile uint32_t CHNL_PRI_ALT_SET;
N  __IO uint32_t CHNL_PRI_ALT_CLR;
X  volatile uint32_t CHNL_PRI_ALT_CLR;
N  __IO uint32_t CHNL_PRIORITY_SET;
X  volatile uint32_t CHNL_PRIORITY_SET;
N  __IO uint32_t CHNL_PRIORITY_CLR;
X  volatile uint32_t CHNL_PRIORITY_CLR;
N}DSP_DMA_TypeDef;
N
N/** @} */ /* End of group Periph_DSP_DMA_TypeDef */
N
N/** @} */ /* End of group Periph_DSP_DMA_Data_Structures */
N
N/** @defgroup Periph_DSP_DMA_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_DSP_DMA_DSP_DMA_DMA_STATUS_Bits DSP_DMA_DMA_STATUS
N  * @{
N  */
N
N#define DSP_DMA_DMA_STATUS_MASTER_ENABLE_Pos    0
N#define DSP_DMA_DMA_STATUS_MASTER_ENABLE        ((uint32_t)0x00000001)
N
N#define DSP_DMA_DMA_STATUS_DMA_ERR_CLR_Pos      1
N#define DSP_DMA_DMA_STATUS_DMA_ERR_CLR          ((uint32_t)0x00000002)
N
N#define DSP_DMA_DMA_STATUS_STATE_Pos            4
N#define DSP_DMA_DMA_STATUS_STATE_Msk            ((uint32_t)0x000000F0)
N
N#define DSP_DMA_DMA_STATUS_CHNLS_MINUS1_Pos     16
N#define DSP_DMA_DMA_STATUS_CHNLS_MINUS1_Msk     ((uint32_t)0x001F0000)
N
N#define DSP_DMA_DMA_STATUS_TEST_STATUS_Pos      28
N#define DSP_DMA_DMA_STATUS_TEST_STATUS_Msk      ((uint32_t)0xF0000000)
N
N
N/** @} */ /* End of group Periph_DSP_DMA_DSP_DMA_DMA_STATUS_Bits */
N
N/** @} */ /* End of group Periph_DSP_DMA_Defines */
N
N/** @defgroup Periph_DSP_DMA_Defines Defines
N  * @{
N  */
N
N/** @defgroup Periph_DSP_DMA_DSP_DMA_DMA_CFG_Bits DSP_DMA_DMA_CFG
N  * @{
N  */
N
N#define DSP_DMA_DMA_CFG_MASTER_ENABLE_Pos       0
N#define DSP_DMA_DMA_CFG_MASTER_ENABLE           ((uint32_t)0x00000001)
N
N#define DSP_DMA_DMA_CFG_CHNL_PROT_CTRL_Pos      5
N#define DSP_DMA_DMA_CFG_CHNL_PROT_CTRL_Msk      ((uint32_t)0x000000E0)
N
N
N/** @} */ /* End of group Periph_DSP_DMA_DSP_DMA_DMA_CFG_Bits */
N
N/** @} */ /* End of group Periph_DSP_DMA_Defines */
N
N/** @} */ /* End of group Periph_DSP_DMA */
N
N/** @} */ /* End of group __1901BC1F_Peripheral_Units */
N
N/** @} */ /* End of group __CMSIS */
N
N#endif /* __1901BC1F_DSP_DMA_DEFS_H */
N
N/******************* (C) COPYRIGHT 2010 Phyton *********************************
N*
N* END OF FILE 1901BC1F_dsp_dma_defs.h */
L 118 ".\inc\1901BC1F.h" 2
N
Ntypedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
N
Ntypedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
N#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
N
Ntypedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
N
N/** @} */ /* End of group __Exported_types */
N
N
N/** @defgroup __Peripheral_Memory_Map Peripheral Memory Map
N  * @{
N  */
N
N#define SPI3_BASE           0x40000000
N#define SPI4_BASE           0x40008000
N#define USB_BASE            0x40010000
N#define EEPROM_BASE         0x40018000
N#define RST_CLK_BASE        0x40020000
N#define DMA_BASE            0x40028000
N#define UART1_BASE          0x40030000
N#define UART2_BASE          0x40038000
N#define SPI1_BASE           0x40040000
N#define SDIO_BASE           0x40048000
N#define I2C_BASE            0x40050000
N#define POWER_BASE          0x40058000
N#define WWDG_BASE           0x40060000
N#define IWDG_BASE           0x40068000
N#define TIMER1_BASE         0x40070000
N#define TIMER2_BASE         0x40078000
N#define TIMER3_BASE         0x40080000
N#define ADC_BASE            0x40088000
N#define DAC_BASE            0x40090000
N#define COMP_BASE           0x40098000
N#define SPI2_BASE           0x400A0000
N#define PORTA_BASE          0x400A8000
N#define PORTB_BASE          0x400B0000
N#define PORTC_BASE          0x400B8000
N#define PORTD_BASE          0x400C0000
N#define PORTE_BASE          0x400C8000
N#define UART3_BASE          0x400D0000
N#define BKP_BASE            0x400D8000
N#define PORTF_BASE          0x400E8000
N#define EXT_BUS_CNTRL_BASE  0x400F0000
N#define DSP_BSP1_BASE       0x30000040
N#define DSP_BSP2_BASE       0x30000050
N#define DSP_BSP3_BASE       0x30000060
N#define DSP_TIM_BASE        0x30000070
N#define DSP_IRQ_BASE        0x30000078
N#define DSP_CRPT_BASE       0x30000080
N#define DSP_ACD_BASE        0x300000A0
N#define DSP_CLK_BASE        0x300000BC
N#define DSP_DMA_BASE        0x300000C0
N
N/** @} */ /* End of group __Peripheral_Memory_Map */
N
N/** @defgroup __Peripheral_declaration Peripheral declaration
N  * @{
N  */
N
N#define SPI3                ((SPI_TypeDef*)     SPI3_BASE)
N#define SPI4                ((SPI_TypeDef*)     SPI4_BASE)
N#define USB                 ((USB_TypeDef*)     USB_BASE)
N#define EEPROM              ((EEPROM_TypeDef*)  EEPROM_BASE)
N#define RST_CLK             ((RST_CLK_TypeDef*) RST_CLK_BASE)
N#define DMA                 ((DMA_TypeDef*)     DMA_BASE)
N#define UART1               ((UART_TypeDef*)    UART1_BASE)
N#define UART2               ((UART_TypeDef*)    UART2_BASE)
N#define SPI1                ((SPI_TypeDef*)     SPI1_BASE)
N#define SDIO                ((SDIO_TypeDef*)    SDIO_BASE)
N#define I2C                 ((I2C_TypeDef*)     I2C_BASE)
N#define POWER               ((POWER_TypeDef*)   POWER_BASE)
N#define WWDG                ((WWDG_TypeDef*)    WWDG_BASE)
N#define IWDG                ((IWDG_TypeDef*)    IWDG_BASE)
N#define TIMER1              ((TIMER_TypeDef*)   TIMER1_BASE)
N#define TIMER2              ((TIMER_TypeDef*)   TIMER2_BASE)
N#define TIMER3              ((TIMER_TypeDef*)   TIMER3_BASE)
N#define ADC                 ((ADC_TypeDef*)     ADC_BASE)
N#define DAC                 ((DAC_TypeDef*)     DAC_BASE)
N#define COMP                ((COMP_TypeDef*)    COMP_BASE)
N#define SPI2                ((SPI_TypeDef*)     SPI2_BASE)
N#define PORTA               ((PORT_TypeDef*)    PORTA_BASE)
N#define PORTB               ((PORT_TypeDef*)    PORTB_BASE)
N#define PORTC               ((PORT_TypeDef*)    PORTC_BASE)
N#define PORTD               ((PORT_TypeDef*)    PORTD_BASE)
N#define PORTE               ((PORT_TypeDef*)    PORTE_BASE)
N#define UART3               ((UART_TypeDef*)    UART3_BASE)
N#define BKP                 ((BKP_TypeDef*)     BKP_BASE)
N#define PORTF               ((PORT_TypeDef*)    PORTF_BASE)
N#define EXT_BUS_CNTRL       ((EXT_BUS_CNTRL_TypeDef*)EXT_BUS_CNTRL_BASE)
N#define DSP_BSP1            ((DSP_BSP_TypeDef*) DSP_BSP1_BASE)
N#define DSP_BSP2            ((DSP_BSP_TypeDef*) DSP_BSP2_BASE)
N#define DSP_BSP3            ((DSP_BSP_TypeDef*) DSP_BSP3_BASE)
N#define DSP_TIM             ((DSP_TIM_TypeDef*) DSP_TIM_BASE)
N#define DSP_IRQ             ((DSP_IRQ_TypeDef*) DSP_IRQ_BASE)
N#define DSP_CRPT            ((DSP_CRPT_TypeDef*)DSP_CRPT_BASE)
N#define DSP_ACD             ((DSP_ACD_TypeDef*) DSP_ACD_BASE)
N#define DSP_CLK             ((DSP_CLK_TypeDef*) DSP_CLK_BASE)
N#define DSP_DMA             ((DSP_DMA_TypeDef*) DSP_DMA_BASE)
N
N/** @} */ /* End of group __Peripheral_declaration */
N
N/** @} */ /* End of group __1901BC1F */
N
N/** @} */ /* End of group __CMSIS */
N
N#endif /* __1901BC1F_H */
N
N/******************* (C) COPYRIGHT 2010 Phyton *********************************
N*
N* END OF FILE 1901BC1F.h */
L 67 "config.h" 2
N#include "ethconfig.c"
L 1 "ethconfig.c" 1
N
N/*
NКонфигурирование контроллера Ethernet и функции для обмена данными по параллельному интерфейсу.
N*/
N
Nvoid EthCfg(void);                                  //функция конфигурирования контроллера 5600ВГ1У
N																			  
Nint Write_Tx_Descriptor(unsigned short,_tx_current_descriptor*); //функция записи дескриптора передатчика
Nunsigned short Read_Tx_Descriptor(_tx_descriptor*); //функция чтения дескриптора передатчика
N
Nint Ready_Rx_Descriptor(_rx_descriptor*);           //функция записи дескриптора приемника
Nunsigned short Read_Rx_Descriptor(_rx_descriptor*); //функция чтения дескриптора приемника
N
Nunsigned short Read_Packet_Start_Address(_rx_descriptor*);     //функция чтения стартового адреса принятого пакета
Nunsigned short Read_Packet_Length(_rx_descriptor*);            //функция чтения длины пакета
N
N//--------------------------------------------------------------------------------------
N//Функция для инициализации Ethernet-контроллера 5600ВГ1У
N//Параметр:	нет
N//Возвращаемых значений нет
N//--------------------------------------------------------------------------------------
Nvoid EthCfg()
N{
N	int i;
N
N		Ethernet->GCTRL = 0x8000;	//Reset 5600VG1U        
X		((_ethernet *)0x60007F00)->GCTRL = 0x8000;	
N		for(i=0;i<1000;i++){}		//Little delay
N		Ethernet->GCTRL = 0x4382;						   	
X		((_ethernet *)0x60007F00)->GCTRL = 0x4382;						   	
N		Ethernet->MinFrame = 0x0040;
X		((_ethernet *)0x60007F00)->MinFrame = 0x0040;
N    	Ethernet->CollConfig = 0;
X    	((_ethernet *)0x60007F00)->CollConfig = 0;
N    	Ethernet->IPGTx = 0x000A;
X    	((_ethernet *)0x60007F00)->IPGTx = 0x000A;
N    	Ethernet->MAC_ADDR_T = 0x1B0A;
X    	((_ethernet *)0x60007F00)->MAC_ADDR_T = 0x1B0A;
N    	Ethernet->MAC_ADDR_M = 0x3D2C;
X    	((_ethernet *)0x60007F00)->MAC_ADDR_M = 0x3D2C;
N    	Ethernet->MAC_ADDR_H = 0x5F4E;
X    	((_ethernet *)0x60007F00)->MAC_ADDR_H = 0x5F4E;
N        Ethernet->PHY_CTRL = 0x31D0;
X        ((_ethernet *)0x60007F00)->PHY_CTRL = 0x31D0;
N		Ethernet->MAC_CTRL = 0x0200;  //Receive broadcast packet and packet with my MAC-address, littel endian ON
X		((_ethernet *)0x60007F00)->MAC_CTRL = 0x0200;  
N}
N
N//--------------------------------------------------------------------------------------
N//Функция для подготовки дескрипторов передатчика к отправке пакетов
N//Параметр:	PacketLen - размер пакета в байтах,
N//			TxCurrentDesc - указатель на текущий дескриптор отправляемых пакетов
N//Возвращаемых значений нет
N//--------------------------------------------------------------------------------------
Nint Write_Tx_Descriptor(unsigned short PacketLen, _tx_current_descriptor* TxCurrentDesc)
N{
N	unsigned int* MyDesc;
N	MyDesc = (unsigned int*)(TxCurrentDesc->TxCurrentDescriptor->StartAddress);
N
N	*(MyDesc+1) = PacketLen;
N	*(MyDesc+3) = (TxCurrentDesc->FirstEmptyWord>>2)&0x0000FFFF;
N
N	if(TxCurrentDesc->TxCurrentDescriptor->LastDesc == 1) *MyDesc = 0xC000;
N	else *MyDesc = 0x8000;
N
N	TxCurrentDesc->FirstEmptyWord += (PacketLen/2)<<2;	//адрес первого свободного 16-разрядного слова в буфере
N												//сдвг PacketLen на 1 разряд, так как в передаваемом пакете
N												//необходимо указывать размер в байтах, а в буфере - 16-разрядные слова!
N	if(TxCurrentDesc->FirstEmptyWord > 0x60005FFC)
N	{
N		TxCurrentDesc->FirstEmptyWord -= 0x00006000;
N		TxCurrentDesc->FirstEmptyWord |= 0x60004000;
N	}
N    return 0;
N}
N
N//--------------------------------------------------------------------------------------
N//Функция для определения статуса отправляемого пакета
N//Параметр:	TxDesc - указатель на дескриптор отправляемых пакетов
N//Возвращает:	1 - пакет не отправлен
N//				0 - пакет отправлен 
N//--------------------------------------------------------------------------------------
Nunsigned short Read_Tx_Descriptor(_tx_descriptor* TxDesc)
N{
N		unsigned int* MyDesc;
N		MyDesc = (unsigned int*)(TxDesc->StartAddress);
N        if((*MyDesc & 0x8000) == 0x8000) return 1;            //пакет не отправлен
N        else return 0;                                              //пакет отправлен
N}
N
N//--------------------------------------------------------------------------------------
N//Функция для установки признака готовности к приему пакета дескриптором принимаемых пакетв
N//Параметр:	RxDesc - указатель на дескриптор принимаемых пакетов
N//Возвращает:	0
N//--------------------------------------------------------------------------------------
Nint Ready_Rx_Descriptor(_rx_descriptor* RxDesc)
N{
N		unsigned int* MyDesc;
N		MyDesc = (unsigned int*)(RxDesc->StartAddress);
N		if(RxDesc->LastDesc == 1) *MyDesc = 0xC000;	//установка готовности дескриптора к приему пакета
N		else *MyDesc = 0x8000;						//установка готовности дескриптора к приему пакета
N        return 0;
N}
N
N//--------------------------------------------------------------------------------------
N//Функция для определения наличия принятого пакета
N//Параметр:	RxDesc - указатель на дескриптор принимаемых пакетов
N//Возвращает:	1 - пакет не принят
N//				0 - пакет принят
N//--------------------------------------------------------------------------------------
Nunsigned short Read_Rx_Descriptor(_rx_descriptor* RxDesc)
N{
N		unsigned int* RDescPointer;
N		RDescPointer = (unsigned int*)RxDesc->StartAddress;
N        if( (*RDescPointer & 0x8000) == 0x8000) return 1;	
N        else return 0;                                      
N}
N
N//--------------------------------------------------------------------------------------
N//Функция для получения размера приянтого пакета
N//Параметр:	RxDesc - указатель на дескриптор принимаемых пакетов
N//Возвращает:	размер пакета в байтах
N//--------------------------------------------------------------------------------------
Nunsigned short Read_Packet_Length(_rx_descriptor* RxDesc)
N{
N		unsigned int* RDescPointer;
N		RDescPointer = (unsigned int*)(RxDesc->StartAddress + 4);		//получим адрес длины пакета
N        return (unsigned short)(*RDescPointer);       //Temp;
N}
N
N//--------------------------------------------------------------------------------------
N//Функция для получения адреса, по которому расположен пакета в буфере приемника
N//Параметр:	RxDesc - указатель на дескриптор принимаемых пакетов
N//Возвращает:	адрес пакета в буфере
N//--------------------------------------------------------------------------------------
Nunsigned short Read_Packet_Start_Address(_rx_descriptor* RxDesc)
N{
N        unsigned int* RDescPointer;
N		RDescPointer = (unsigned int*)(RxDesc->StartAddress + 12);	//получим адрес стартового адреса пакета
N        return (unsigned short)(*RDescPointer);
N}
N
L 68 "config.h" 2
N
Nvoid ExtBusCfg(void);
Nvoid PortConfig(void);
Nvoid ClkCfg(void);
N
N//--------------------------------------------------------------------------------------
N//Функция для настройки внешней системной шины
N//Параметр:	нет
N//Возвращаемых знаений нет
N//--------------------------------------------------------------------------------------
N__inline void ExtBusCfg()
N{
N	EXT_BUS_CNTRL->EXT_BUS_CONTROL = 0x2002;  //wait state=0 (3 HCLK), RAM mode
X	((EXT_BUS_CNTRL_TypeDef*)0x400F0000)->EXT_BUS_CONTROL = 0x2002;  
N}
N
N//--------------------------------------------------------------------------------------
N//Функция для настройки портов контроллера 1986ВЕ91Т1
N//Параметр:	нет
N//Возвращаемых знаений нет
N//-------------------------------------------------------------------------------------- 
Nvoid PortConfig()
N{
N//Data Bus[0:15]
N		PORTA->ANALOG = 0xFFFF;
X		((PORT_TypeDef*) 0x400A8000)->ANALOG = 0xFFFF;
N		PORTA->PWR = 0xAAAAAAAA;
X		((PORT_TypeDef*) 0x400A8000)->PWR = 0xAAAAAAAA;
N		PORTA->FUNC = 0x55555555;
X		((PORT_TypeDef*) 0x400A8000)->FUNC = 0x55555555;
N
N//OE-WE & Buttons
N		PORTC->ANALOG = 0xFFFF; // OE-WE
X		((PORT_TypeDef*) 0x400B8000)->ANALOG = 0xFFFF; 
N		PORTC->PWR = 0xAAAAAAAA; // OE-WE
X		((PORT_TypeDef*) 0x400B8000)->PWR = 0xAAAAAAAA; 
N		PORTC->FUNC = 0x00000014; // OE-WE
X		((PORT_TypeDef*) 0x400B8000)->FUNC = 0x00000014; 
N//		PORTC->PD   = 0x00000000; // OE-WE//Светодиоды
N//		PORTC->RXTX = 0x0000;
N//		PORTC->OE = 0x0080;
N//LED
N
N        PORTD->RXTX = 0;
X        ((PORT_TypeDef*) 0x400C0000)->RXTX = 0;
N        PORTD->OE = 0x7C00; //PORTD10 - PORTD14 - outputs
X        ((PORT_TypeDef*) 0x400C0000)->OE = 0x7C00; 
N        PORTD->FUNC = 0x00000000; //PORTD - ports
X        ((PORT_TypeDef*) 0x400C0000)->FUNC = 0x00000000; 
N        PORTD->ANALOG = 0xFF00; //PORTD - digital
X        ((PORT_TypeDef*) 0x400C0000)->ANALOG = 0xFF00; 
N        PORTD->PWR = 0xAAAA0000; //PORTD8 - PORTD15 - fast edge
X        ((PORT_TypeDef*) 0x400C0000)->PWR = 0xAAAA0000; 
N
N//Address Bus[0:12]
N		PORTE->ANALOG = 0xFFFF; // CS
X		((PORT_TypeDef*) 0x400C8000)->ANALOG = 0xFFFF; 
N		PORTE->PWR = 0xAAAAAAAA; // CS
X		((PORT_TypeDef*) 0x400C8000)->PWR = 0xAAAAAAAA; 
N		PORTE->RXTX = 0x0000;
X		((PORT_TypeDef*) 0x400C8000)->RXTX = 0x0000;
N		PORTE->OE = 0x0030;
X		((PORT_TypeDef*) 0x400C8000)->OE = 0x0030;
N		PORTE->FUNC = 0x01000000; // CS
X		((PORT_TypeDef*) 0x400C8000)->FUNC = 0x01000000; 
N
N		PORTF->ANALOG = 0xFFFF;
X		((PORT_TypeDef*) 0x400E8000)->ANALOG = 0xFFFF;
N		PORTF->PWR = 0xFFFFFFFF;
X		((PORT_TypeDef*) 0x400E8000)->PWR = 0xFFFFFFFF;
N		PORTF->FUNC = 0x55555555;
X		((PORT_TypeDef*) 0x400E8000)->FUNC = 0x55555555;
N
N		PORTB->RXTX = 0;
X		((PORT_TypeDef*) 0x400B0000)->RXTX = 0;
N        PORTB->OE = 0x8000; //PORTD10 - PORTD14 - outputs
X        ((PORT_TypeDef*) 0x400B0000)->OE = 0x8000; 
N        PORTB->FUNC = 0x00000000; //PORTD - ports
X        ((PORT_TypeDef*) 0x400B0000)->FUNC = 0x00000000; 
N        PORTB->ANALOG = 0xC000; //PORTD - digital
X        ((PORT_TypeDef*) 0x400B0000)->ANALOG = 0xC000; 
N        PORTB->PWR = 0xC0000000; //PORTD8 - PORTD15 - fast edge
X        ((PORT_TypeDef*) 0x400B0000)->PWR = 0xC0000000; 
N}
N
N//--------------------------------------------------------------------------------------
N//Функция для настройки тактовых сигналов контроллера 1986ВЕ91Т1
N//Параметр:	нет
N//Возвращаемых знаений нет
N//-------------------------------------------------------------------------------------- 
Nvoid ClkCfg()
N{
N        RST_CLK->HS_CONTROL = 0x00000001;
X        ((RST_CLK_TypeDef*) 0x40020000)->HS_CONTROL = 0x00000001;
N        while((RST_CLK->CLOCK_STATUS&0x00000004)!=0x00000004){}
X        while((((RST_CLK_TypeDef*) 0x40020000)->CLOCK_STATUS&0x00000004)!=0x00000004){}
N		RST_CLK->CPU_CLOCK = 0x00000102;
X		((RST_CLK_TypeDef*) 0x40020000)->CPU_CLOCK = 0x00000102;
N		//RST_CLK->PER_CLOCK = 0x63E00018;
N		RST_CLK->PER_CLOCK = 0xffffffff;
X		((RST_CLK_TypeDef*) 0x40020000)->PER_CLOCK = 0xffffffff;
N}
N
N#endif /*__CONFIG_H_*/
N
L 62 "main.c" 2
N	 
N//Структура для работы с принятыми Ethernet-пакетами
Ntypedef struct
N{
N        unsigned char Data[1600];       //Данные пакета
N        unsigned short Length;          //Размер принятого пакета
N        unsigned short Address;         //Адрес, по которому расположен пакет в буфере приемника
N        unsigned char Remote_IP[4];     //удаленный IP-адрес (IP-адрес отправителя принятого пакета)
N        unsigned char Remote_MAC[6];    //удаленный MAC-адрес (MAC-адрес отправителя принятого пакета)
N
N#if PRINTSTATUSON
X#if 1
N		unsigned int CounterTxPacket;	//Счетчик отправленных пакетов
N		unsigned int CounterRxPacket;	//Счетчик принятых пакетов
N#endif	//PRINTSTATUSON
N
N} _ethernet_packet;
N						   
Nint Read_Packet(_ethernet_packet*);			//функция для считывания принятого пакета
Nunsigned short CheckSum_IP(_ethernet_packet*);		//функция для вычисления контрольной суммы IP-пакета
Nunsigned short CheckSum_ICMP(_ethernet_packet*);	//функция для вычисления контрольной суммы ICMP-пакета
Nvoid InitTxDescriptor(void);						//функция инициализации дескрипторов отправляемых пакетов
Nvoid InitRxDescriptor(void);						//функция инициализации дескрипторов принимаемых пакетов
Nint Answear_ARP(_ethernet_packet*);					//функция формирования ответа на ARP-запрос
Nint Answear_ICMP(_ethernet_packet*,unsigned char*);	//функция формирования ответа на ICMP-запрос
N
N#if PRINTSTATUSON
X#if 1
Nvoid Request_Status(_ethernet_packet*);
N#endif	//PRINTSTATUSON
N
N//массив дескрипторов отправляемых пакетов
N_tx_descriptor ATxDescriptor[32] =  {{0x60006000,0x0000,0,0,0,0},{0x60006010,0x0000,0,0,0,0},{0x60006020,0x0000,0,0,0,0},{0x60006030,0x0000,0,0,0,0},
N									 {0x60006040,0x0000,0,0,0,0},{0x60006050,0x0000,0,0,0,0},{0x60006060,0x0000,0,0,0,0},{0x60006070,0x0000,0,0,0,0},
N									 {0x60006080,0x0000,0,0,0,0},{0x60006090,0x0000,0,0,0,0},{0x600060A0,0x0000,0,0,0,0},{0x600060B0,0x0000,0,0,0,0},
N									 {0x600060C0,0x0000,0,0,0,0},{0x600060D0,0x0000,0,0,0,0},{0x600060E0,0x0000,0,0,0,0},{0x600060F0,0x0000,0,0,0,0},
N									 {0x60006100,0x0000,0,0,0,0},{0x60006110,0x0000,0,0,0,0},{0x60006120,0x0000,0,0,0,0},{0x60006130,0x0000,0,0,0,0},
N									 {0x60006140,0x0000,0,0,0,0},{0x60006150,0x0000,0,0,0,0},{0x60006160,0x0000,0,0,0,0},{0x60006170,0x0000,0,0,0,0},
N									 {0x60006180,0x0000,0,0,0,0},{0x60006190,0x0000,0,0,0,0},{0x600061A0,0x0000,0,0,0,0},{0x600061B0,0x0000,0,0,0,0},
N									 {0x600061C0,0x0000,0,0,0,0},{0x600061D0,0x0000,0,0,0,0},{0x600061E0,0x0000,0,0,0,0},{0x600061F0,0x4000,0,0,0,1}};
N
N//массив дескрипторов принимаемых пакетов
N_rx_descriptor	ARxDescriptor[32] = {{0x60002000,0x8000,0,0,0,0},{0x60002010,0x8000,0,0,0,0},{0x60002020,0x8000,0,0,0,0},{0x60002030,0x8000,0,0,0,0},
N									 {0x60002040,0x8000,0,0,0,0},{0x60002050,0x8000,0,0,0,0},{0x60002060,0x8000,0,0,0,0},{0x60002070,0x8000,0,0,0,0},
N									 {0x60002080,0x8000,0,0,0,0},{0x60002090,0x8000,0,0,0,0},{0x600020A0,0x8000,0,0,0,0},{0x600020B0,0x8000,0,0,0,0},
N									 {0x600020C0,0x8000,0,0,0,0},{0x600020D0,0x8000,0,0,0,0},{0x600020E0,0x8000,0,0,0,0},{0x600020F0,0x8000,0,0,0,0},
N									 {0x60002100,0x8000,0,0,0,0},{0x60002110,0x8000,0,0,0,0},{0x60002120,0x8000,0,0,0,0},{0x60002130,0x8000,0,0,0,0},
N									 {0x60002140,0x8000,0,0,0,0},{0x60002150,0x8000,0,0,0,0},{0x60002160,0x8000,0,0,0,0},{0x60002170,0x8000,0,0,0,0},
N									 {0x60002180,0x8000,0,0,0,0},{0x60002190,0x8000,0,0,0,0},{0x600021A0,0x8000,0,0,0,0},{0x600021B0,0x8000,0,0,0,0},
N									 {0x600021C0,0x8000,0,0,0,0},{0x600021D0,0x8000,0,0,0,0},{0x600021E0,0x8000,0,0,0,0},{0x600021F0,0xC000,0,0,0,1}};
N
N_tx_current_descriptor TxCurrentDesc;	//экземпляр структуры _tx_current_descriptor
N_rx_current_descriptor RxCurrentDesc;	//экземпляр структуры _rx_current_descriptor
N_ethernet_packet Packet;				//экземпляр структуры _ethernet_packet
Nunsigned short Temp, TypeOfProtocol;	//Temp - временная переменная, TypeOfProtocol - тип протокола пакета, вложенного в Eth2 пакет.
Nunsigned char My_IP[4], My_MAC[6];		//переменные, содржащие наш IP и MAC-адреса
Nunsigned char Receive_IP[4];			//IP-адрес принятого пакета
Nunsigned char ICMP_Packet[1500];  		//буфер для формирования ответного ICMP-пакета.
N
N#if PRINTSTATUSON
X#if 1
N_ethernet* MyEth;						//указатель на структуру _ethernet (введен для просмотр состояния регистров Ethernet-контроллера 5600ВГ1У)
N#endif	//PRINTSTATUSON
N
N
N//unsigned int *MyPtrTx, *MyPtrRx, *ptrTD, *ptrRD;
N//unsigned int adr, len, i;
N//unsigned int ArrayRead[1000];
N
Nint main()
N{
N        ClkCfg();		
N        PortConfig();	
N		ExtBusCfg();	
N
N#if	PRINTSTATUSON
X#if	1
N		MyEth = Ethernet;
X		MyEth = ((_ethernet *)0x60007F00);
N#endif	//PRINTSTATUSON
N
N        My_IP[0] =  0xC0;
N        My_IP[1] =  0xA8;
N        My_IP[2] =  0x01;
N        My_IP[3] =  0x57;
N
N        My_MAC[0] = 0x0A;
N        My_MAC[1] = 0x1B;
N        My_MAC[2] = 0x2C;
N        My_MAC[3] = 0x3D;
N        My_MAC[4] = 0x4E;
N        My_MAC[5] = 0x5F;
N
N		InitTxDescriptor();	
N		InitRxDescriptor();
N
N		EthCfg();
N		PORTB->PORTx_SET=0x8000;
X		((PORT_TypeDef*) 0x400B0000)->PORTx_SET=0x8000;
N
N#if	PRINTSTATUSON
X#if	1
N		Packet.CounterRxPacket = 0;
N		Packet.CounterTxPacket = 0;
N#endif	//PRINTSTATUSON
N
N//модуль Ethernet сконфигурирован
N        while(1)
N        {
N                if(Read_Rx_Descriptor(RxCurrentDesc.RxCurrentDescriptor) == 0) //проверка наличия принятого пакета
N                {
N                        PORTD->RXTX |= 1 << 11;
X                        ((PORT_TypeDef*) 0x400C0000)->RXTX |= 1 << 11;
N
N                        Packet.Length = Read_Packet_Length(RxCurrentDesc.RxCurrentDescriptor);
N                        Packet.Address = Read_Packet_Start_Address(RxCurrentDesc.RxCurrentDescriptor);
N                        Read_Packet(&Packet);				   //считали полученный пакет
N
N						Ready_Rx_Descriptor(RxCurrentDesc.RxCurrentDescriptor);
N
N#if	PRINTSTATUSON
X#if	1
N						Packet.CounterRxPacket++;
N#endif	//PRINTSTATUSON						
N
N						Ethernet->RXBF_HEAD = (Ethernet->RXBF_TAIL-1)&0x07FF;
X						((_ethernet *)0x60007F00)->RXBF_HEAD = (((_ethernet *)0x60007F00)->RXBF_TAIL-1)&0x07FF;
N
N                        TypeOfProtocol = (Packet.Data[12]<<8)|Packet.Data[13];
N
N                        switch(TypeOfProtocol) //0x0006 //слова в памяти разбиты по 2 байта! (считывать массив кратный 2 байтам!)
N                        {
N                                case 0x0806:    //receive ARP-packet
N                                        Receive_IP[0] = Packet.Data[38];
N                                        Receive_IP[1] = Packet.Data[39];
N                                        Receive_IP[2] = Packet.Data[40];
N                                        Receive_IP[3] = Packet.Data[41];
N
N                                        if( (Receive_IP[0] == My_IP[0])&&(Receive_IP[1] == My_IP[1])&&(Receive_IP[2] == My_IP[2])&&(Receive_IP[3] == My_IP[3]))         //полное совпадение IP в пакете и нашего. Надо отвечать
N                                        {
N                                                        Packet.Remote_IP[0] = Packet.Data[28];
N                                                        Packet.Remote_IP[1] = Packet.Data[29];
N                                                        Packet.Remote_IP[2] = Packet.Data[30];
N                                                        Packet.Remote_IP[3] = Packet.Data[31];
N
N                                                        Packet.Remote_MAC[0] = Packet.Data[22];
N                                                        Packet.Remote_MAC[1] = Packet.Data[23];
N                                                        Packet.Remote_MAC[2] = Packet.Data[24];
N                                                        Packet.Remote_MAC[3] = Packet.Data[25];
N                                                        Packet.Remote_MAC[4] = Packet.Data[26];
N                                                        Packet.Remote_MAC[5] = Packet.Data[27];
N
N                                                        Answear_ARP(&Packet);
N                                        }
N                                        PORTD->RXTX &= 0xF7FF;
X                                        ((PORT_TypeDef*) 0x400C0000)->RXTX &= 0xF7FF;
N                                        break;
N
N                                case 0x0800:    //receive IP-packet     //реализуем ICMP-протокол
N                                        Receive_IP[0] = Packet.Data[30];
N                                        Receive_IP[1] = Packet.Data[31];
N                                        Receive_IP[2] = Packet.Data[32];
N                                        Receive_IP[3] = Packet.Data[33];
N
N                                        if((Receive_IP[0] == My_IP[0])&&(Receive_IP[1] == My_IP[1])&&(Receive_IP[2] == My_IP[2])&&(Receive_IP[3] == My_IP[3]))  //получили IP-пакет с нашим IP адресом
N                                        {
N                                                        Temp = CheckSum_IP(&Packet);
N                                                        if(Temp == ((Packet.Data[24] << 8)&0xFF00|Packet.Data[25]))  //если контрольная сумма IP-протокола пакета и вычисленная совпадают, то работаем дальше, иначе откидываем пакет
N                                                        {
N                                                                Packet.Remote_IP[0] = Packet.Data[26];
N                                                                Packet.Remote_IP[1] = Packet.Data[27];
N                                                                Packet.Remote_IP[2] = Packet.Data[28];
N                                                                Packet.Remote_IP[3] = Packet.Data[29];
N
N                                                                Packet.Remote_MAC[0] = Packet.Data[6];
N                                                                Packet.Remote_MAC[1] = Packet.Data[7];
N                                                                Packet.Remote_MAC[2] = Packet.Data[8];
N                                                                Packet.Remote_MAC[3] = Packet.Data[9];
N                                                                Packet.Remote_MAC[4] = Packet.Data[10];
N                                                                Packet.Remote_MAC[5] = Packet.Data[11];
N
N                                                                //проверить следующий протокол (ICMP)
N                                                                if(Packet.Data[23] == 0x01)     //далее следует ICMP-протокол
N                                                                {																			
N																		if(Packet.Data[34] == 0x08) //приняли echo request
N                                                                        {
N                                                                                Temp = CheckSum_ICMP(&Packet);
N                                                                                if(Temp == ((Packet.Data[36] << 8)&0xFF00|Packet.Data[37]))	//проверка совпадения контрольной суммы ICMP-пакета и вычисленной
N                                                                                {
N                                                                                        Answear_ICMP(&Packet, ICMP_Packet);
N                                                                                }
N                                                                        }
N                                                                }
N                                                        }
N                                        }
N                                        PORTD->RXTX &= 0xF7FF;
X                                        ((PORT_TypeDef*) 0x400C0000)->RXTX &= 0xF7FF;
N                                        break;
N                        }
N                } //if(Read_Rx_Descriptor(RxCurrentDescriptor) == 0) //we receive Eth. packet
N                PORTD->RXTX &= 0xF7FF;
X                ((PORT_TypeDef*) 0x400C0000)->RXTX &= 0xF7FF;
N
N				//переход к следующему дескриптору
N				RxCurrentDesc.RxCurrentDescriptor++;
N				RxCurrentDesc.Number++;
N				if(RxCurrentDesc.Number == NUMRXDESCRIPTOR)
X				if(RxCurrentDesc.Number == 16)
N				{
N					RxCurrentDesc.RxCurrentDescriptor = ARxDescriptor;
N					RxCurrentDesc.Number = 0;	
N				}
N        }
N}
N
N//--------------------------------------------------------------------------------------
N//Функция для вычисления контрольной суммы IP-пакета
N//Параметр:	указатель на принятый Ethernet-пакет
N//Возвращает контрольную сумму IP-пакета
N//--------------------------------------------------------------------------------------
Nunsigned short CheckSum_IP(_ethernet_packet* Dt)
N{
N        unsigned long Temp, Check = 0;
N        for(Temp = 0; Temp < 20; Temp += 2)
N        {
N                if(Temp == 10) continue;
N                else Check += ((Dt->Data[Temp + 14] << 8)&0xFF00)|Dt->Data[Temp + 15];
N        }
N        Check = (Check >> 16) + (Check & 0xFFFF);
N        return (unsigned short)(~Check);
N}
N//--------------------------------------------------------------------------------------
N//Функция для вычисления контрольной суммы ICMP-пакета
N//Параметр:	указатель на принятый Ethernet-пакет
N//Возвращает контрольную сумму ICMP-пакета
N//--------------------------------------------------------------------------------------
Nunsigned short CheckSum_ICMP(_ethernet_packet* Dt)
N{
N        unsigned long Temp, Check = 0;
N        for(Temp = 0; Temp < Dt->Length - 38; Temp += 2)      //реализовано для пакета ICMP объёмом до 1450 байт
N        {                                                     //Dt->Length - 38,т.к. 34 байта - это Eth2 и IP заголовки, 4 байта - CRС32 Eth2 пакета
N                if(Temp == 2) continue;
N                else Check += ((Dt->Data[Temp + 34] << 8)&0xFF00)|Dt->Data[Temp + 35];
N        }
N        Check = (Check >> 16) + (Check & 0xFFFF);
N        return (unsigned short)(~Check);
N}
N//--------------------------------------------------------------------------------------
N//Функция для считывания пакета
N//Параметр:	указатель на принятый Ethernet-пакет
N//Возвращает 0
N//--------------------------------------------------------------------------------------
Nint Read_Packet(_ethernet_packet* Dt)
N{
N        unsigned short Temp,Val;
N		unsigned int* MyPointer;
N		MyPointer = (unsigned int*)((unsigned int)RxBuffer + (unsigned int)(Dt->Address<<2));
X		MyPointer = (unsigned int*)((unsigned int)((unsigned int *)0x60000000) + (unsigned int)(Dt->Address<<2));
N		for(Temp=0;Temp<Dt->Length;Temp+=2)
N		{
N			Val = *MyPointer++;
N			Dt->Data[Temp] = (unsigned char)Val;
N			Dt->Data[Temp+1] = (unsigned char)(Val>>8);
N			if( ((int)MyPointer & 0x00002000) == 0x00002000) MyPointer = RxBuffer;
X			if( ((int)MyPointer & 0x00002000) == 0x00002000) MyPointer = ((unsigned int *)0x60000000);
N		}
N        if((Dt->Length & 0x0001) == 1)  //если пакет содержит нечетное кол-во байт, то необходимо занулить предпоследний
N                                        //считанный байт в буфере, так как он влияет на контрольную сумму ICMP-пакета.
N        {
N                Dt->Data[Dt->Length-4] = 0;
N        }
N		
N        return 0;
N}
N
N//--------------------------------------------------------------------------------------
N//Функция для формирования ответа на ARP-запрос
N//Параметр:	указатель на принятый Ethernet-пакет
N//Возвращает 0
N//--------------------------------------------------------------------------------------
Nint Answear_ARP(_ethernet_packet* Dt)
N{
N        unsigned char Send[42];
N        unsigned short Temp;
N		unsigned int* MyPointer;
N	
N        while(Read_Tx_Descriptor(TxCurrentDesc.TxCurrentDescriptor) != 0)
N		{
N			TxCurrentDesc.TxCurrentDescriptor++;
N			TxCurrentDesc.Number++;
N			if(TxCurrentDesc.Number == NUMTXDESCRIPTOR)
X			if(TxCurrentDesc.Number == 16)
N			{
N				TxCurrentDesc.Number = 0;
N				TxCurrentDesc.TxCurrentDescriptor = ATxDescriptor;
N			}	
N		}
N		
N        //первые 6 байт - удаленный MAC - адрес
N        Send[0] = Dt->Remote_MAC[0];
N        Send[1] = Dt->Remote_MAC[1];
N        Send[2] = Dt->Remote_MAC[2];
N        Send[3] = Dt->Remote_MAC[3];
N        Send[4] = Dt->Remote_MAC[4];
N        Send[5] = Dt->Remote_MAC[5];
N
N        //далее 6 байт - мой MAC-адрес
N        Send[6] = My_MAC[0];
N        Send[7] = My_MAC[1];
N        Send[8] = My_MAC[2];
N        Send[9] = My_MAC[3];
N        Send[10] = My_MAC[4];
N        Send[11] = My_MAC[5];
N
N        //далее заполняем всё так же как в полученном пакете до 19 байта (включительно)
N        for(Temp = 12; Temp < 20; Temp++)
N        {
N                Send[Temp] = Dt->Data[Temp];
N        }
N
N        //20 и 21 байты - Opcode: для ответа должен быть равен 2
N        Send[21] = 0x02;
N        Send[20] = 0x00;
N
N        //с 22 по 27 (включительно) идет мой MAC
N
N        Send[22] = My_MAC[0];
N        Send[23] = My_MAC[1];
N        Send[24] = My_MAC[2];
N        Send[25] = My_MAC[3];
N        Send[26] = My_MAC[4];
N        Send[27] = My_MAC[5];
N
N        //с 28 по 31 (включительно) идет мой IP
N
N        Send[28] = My_IP[0];
N        Send[29] = My_IP[1];
N        Send[30] = My_IP[2];
N        Send[31] = My_IP[3];
N
N        //с 32 по 37 (включительно) идет удаленный MAC
N
N        Send[32] = Dt->Remote_MAC[0];
N        Send[33] = Dt->Remote_MAC[1];
N        Send[34] = Dt->Remote_MAC[2];
N        Send[35] = Dt->Remote_MAC[3];
N        Send[36] = Dt->Remote_MAC[4];
N        Send[37] = Dt->Remote_MAC[5];
N
N        //с 38 по 41 (включительно) идет удаленный IP
N
N        Send[38] = Dt->Remote_IP[0];
N        Send[39] = Dt->Remote_IP[1];
N        Send[40] = Dt->Remote_IP[2];
N        Send[41] = Dt->Remote_IP[3];
N		
N		MyPointer = (unsigned int*)TxCurrentDesc.FirstEmptyWord;
N
N		for(Temp=0;Temp<42;Temp+=2)
N		{
N			*MyPointer++ = Send[Temp]|(Send[Temp+1]<<8);
N			if((unsigned int)MyPointer > 0x60005FFC) MyPointer = (unsigned int*)0x60004000;
N		}
N        
N        Write_Tx_Descriptor(0x002A,&TxCurrentDesc);     //42 bytes
N
N 		TxCurrentDesc.TxCurrentDescriptor++;
N		TxCurrentDesc.Number++;
N		if(TxCurrentDesc.Number == NUMTXDESCRIPTOR)
X		if(TxCurrentDesc.Number == 16)
N		{
N			TxCurrentDesc.Number = 0;
N			TxCurrentDesc.TxCurrentDescriptor = ATxDescriptor;
N		}
N
N#if PRINTSTATUSON
X#if 1
N		Packet.CounterTxPacket++;
N#endif	//PRINTSTATUSON
N
N		return 0;
N}
N//--------------------------------------------------------------------------------------
N//Функция для формирования ответа на ICMP-запрос
N//Параметр:	указатель на принятый Ethernet-пакет
N//Возвращает 0
N//--------------------------------------------------------------------------------------
Nint Answear_ICMP(_ethernet_packet* Dt , unsigned char* ICMP_Packet)
N{
N        unsigned short Temp;
N		unsigned int* MyPointer;
N
N        while(Read_Tx_Descriptor(TxCurrentDesc.TxCurrentDescriptor) != 0)
N		{
N			TxCurrentDesc.TxCurrentDescriptor++;
N			TxCurrentDesc.Number++;
N			if(TxCurrentDesc.Number == NUMTXDESCRIPTOR)
X			if(TxCurrentDesc.Number == 16)
N			{
N				TxCurrentDesc.Number = 0;
N				TxCurrentDesc.TxCurrentDescriptor = ATxDescriptor;
N			}
N		}
N		
N        //Remote MAC-Address
N        ICMP_Packet[0] = Dt->Remote_MAC[0];
N        ICMP_Packet[1] = Dt->Remote_MAC[1];
N        ICMP_Packet[2] = Dt->Remote_MAC[2];
N        ICMP_Packet[3] = Dt->Remote_MAC[3];
N        ICMP_Packet[4] = Dt->Remote_MAC[4];
N        ICMP_Packet[5] = Dt->Remote_MAC[5];
N
N        //My MAC-Address
N        ICMP_Packet[6] = My_MAC[0];
N        ICMP_Packet[7] = My_MAC[1];
N        ICMP_Packet[8] = My_MAC[2];
N        ICMP_Packet[9] = My_MAC[3];
N        ICMP_Packet[10] = My_MAC[4];
N        ICMP_Packet[11] = My_MAC[5];
N
N        //IP-protocol
N        ICMP_Packet[12] = 0x08;
N        ICMP_Packet[13] = 0x00;
N//Закнчили формировать Eth2-пакет
N
N//Формируем IP-пакет
N        //Field of IP-protocol
N        for(Temp = 14; Temp < 24; Temp++)
N        {
N                ICMP_Packet[Temp] = Dt->Data[Temp];
N        }
N        ICMP_Packet[26] = Dt->Data[30];
N        ICMP_Packet[27] = Dt->Data[31];
N        ICMP_Packet[28] = Dt->Data[32];
N        ICMP_Packet[29] = Dt->Data[33];
N        //Remote IP
N        ICMP_Packet[30] = Dt->Data[26];
N        ICMP_Packet[31] = Dt->Data[27];
N        ICMP_Packet[32] = Dt->Data[28];
N        ICMP_Packet[33] = Dt->Data[29];
N
N        Temp = CheckSum_IP(Dt);
N
N        //IP CheckSum
N        ICMP_Packet[24] = (unsigned char)(Temp >> 8);
N        ICMP_Packet[25] = (unsigned char)Temp;
N
N//Закнчили формировать IP-пакет
N//Формируем ICMP-пакет
N        ICMP_Packet[34] = 0x00; //Echo reply
N        ICMP_Packet[35] = 0x00;
N
N        Dt->Data[34] = 0x00;
N        Dt->Data[35] = 0x00;
N
N        Temp = CheckSum_ICMP(Dt);
N        ICMP_Packet[36] = (unsigned char)(Temp >> 8);
N        ICMP_Packet[37] = (unsigned char)Temp;
N
N        for(Temp = 38; Temp < Dt->Length - 4; Temp++)
N        {
N                ICMP_Packet[Temp] = Dt->Data[Temp];
N        }
N
N		MyPointer = (unsigned int*)TxCurrentDesc.FirstEmptyWord;
N
N        if((Dt->Length & 0x0001) == 1)
N        {
N                ICMP_Packet[Dt->Length - 4] = Dt->Data[Dt->Length - 4];
N                for(Temp=0;Temp<Dt->Length - 3;Temp+=2)
N				{
N					*MyPointer++ = ICMP_Packet[Temp]|(ICMP_Packet[Temp+1]<<8);
N					if((unsigned int)MyPointer > 0x60005FFC) MyPointer = (unsigned int*)0x60004000;
N				}
N        }
N        else
N        {
N                for(Temp=0;Temp<Dt->Length - 4;Temp+=2)
N				{
N					*MyPointer++ = ICMP_Packet[Temp]|(ICMP_Packet[Temp+1]<<8);
N					if((unsigned int)MyPointer > 0x60005FFC) MyPointer = (unsigned int*)0x60004000;
N				}
N        }
N//Закончили формировать ICMP-пакет
N
N        Write_Tx_Descriptor(Dt->Length-4,&TxCurrentDesc);     //74 bytes
N
N		TxCurrentDesc.TxCurrentDescriptor++;
N		TxCurrentDesc.Number++;
N		if(TxCurrentDesc.Number == NUMTXDESCRIPTOR)
X		if(TxCurrentDesc.Number == 16)
N		{
N			TxCurrentDesc.Number = 0;
N			TxCurrentDesc.TxCurrentDescriptor = ATxDescriptor;
N		}
N
N#if PRINTSTATUSON
X#if 1
N		Packet.CounterTxPacket++;
N#endif	//PRINTSTATUSON
N
N        return 0;
N}
N//--------------------------------------------------------------------------------------
N//Функция для инициализации дескрипторов передаваемых пакетов
N//Параметр:	нет
N//Возвращаемых значений нет
N//--------------------------------------------------------------------------------------
Nvoid InitTxDescriptor()
N{
N	unsigned int* TDescPointer;
N
N	TxCurrentDesc.TxCurrentDescriptor = ATxDescriptor;
N	TxCurrentDesc.FirstEmptyWord = 0x60004000;
N
N	for(Temp=0;Temp<NUMTXDESCRIPTOR;Temp++)
X	for(Temp=0;Temp<16;Temp++)
N	{
N		TDescPointer = (unsigned int*)(TxCurrentDesc.TxCurrentDescriptor->StartAddress);
N		*TDescPointer = TxCurrentDesc.TxCurrentDescriptor->Status;
N		TxCurrentDesc.TxCurrentDescriptor++;
N	}
N
N	TxCurrentDesc.TxCurrentDescriptor--;
N	TxCurrentDesc.TxCurrentDescriptor->LastDesc = 1;	//установка признака последнего дескриптора
N	TDescPointer = (unsigned int*)(TxCurrentDesc.TxCurrentDescriptor->StartAddress);
N	*TDescPointer = 0x4000;								//последний обрабатываемый дескриптор
N
N	TxCurrentDesc.Number = 0;
N	TxCurrentDesc.TxCurrentDescriptor = ATxDescriptor;
N}
N//--------------------------------------------------------------------------------------
N//Функция для инициализации дескрипторов принимаемых пакетов
N//Параметр:	нет
N//Возвращаемых значений нет
N//--------------------------------------------------------------------------------------
Nvoid InitRxDescriptor()
N{
N	unsigned int* RDescPointer;
N
N	RxCurrentDesc.RxCurrentDescriptor = ARxDescriptor;
N
N	for(Temp=0;Temp<NUMRXDESCRIPTOR;Temp++)
X	for(Temp=0;Temp<16;Temp++)
N	{
N		RDescPointer = (unsigned int*)(RxCurrentDesc.RxCurrentDescriptor->StartAddress);
N		*RDescPointer = RxCurrentDesc.RxCurrentDescriptor->Status;
N		RxCurrentDesc.RxCurrentDescriptor++;
N	}
N
N	RxCurrentDesc.RxCurrentDescriptor--;
N	RxCurrentDesc.RxCurrentDescriptor->LastDesc = 1;	//установка признака последнего дескриптора
N	RDescPointer = (unsigned int*)(RxCurrentDesc.RxCurrentDescriptor->StartAddress);
N	*RDescPointer = 0xC000;								//последний обрабатываемый дескриптор
N
N	RxCurrentDesc.Number = 0;
N	RxCurrentDesc.RxCurrentDescriptor = ARxDescriptor;
N}
N
N
N
