
#ifndef __CONFIG_C
#define __CONFIG_C

#include "opora.h"
#include "config.h"

//--- Clock configuration ---
void ClkConfig()
{
#ifdef REVISION_2
	
#ifdef HSE2_GEN
	RST_CLK->HS_CONTROL=0x0000000D;					//HSE On, Oscillator mode; HSE2 On, Generator mode
#else
	RST_CLK->HS_CONTROL=0x00000005;					//HSE On, Oscillator mode; HSE2 On, Oscillator mode
#endif	//HSE2_GEN

	while((RST_CLK->CLOCK_STATUS&0x0C)!=0x0C);		//Wait until HSE and HSE2 not ready
	RST_CLK->CPU_CLOCK=0x00000002;					//HSE=8 MHz
	RST_CLK->PLL_CONTROL=(11<<8)|(1<<2);			//PLL CPU On, PLL_MULL=11
	while((RST_CLK->CLOCK_STATUS&0x02)!=0x02);		//wait until PLL CPU not ready
	RST_CLK->PER_CLOCK|=0x08;						//EEPROM_CNTRL Clock enable
	EEPROM->CMD=3<<3;								//Delay=4	 
	RST_CLK->PER_CLOCK&=(~0x08);					//EEPROM_CNTRL Clock enable
	RST_CLK->CPU_CLOCK|=0x00000106;					//CPU Clock = 12*8MHz = 96 MHz
	RST_CLK->ETH_CLOCK=(1<<24)|(3<<28)|(1<<27);		//PHY_CLK_SEL = HSE2, ETH_CLK_EN=1, PHY_CLK_EN=1, ETH_CLK = 25MHz
#else
	RST_CLK->HS_CONTROL=0x00000003;					//HSE - On; Gen mode On
	while((RST_CLK->CLOCK_STATUS&0x04)!=0x04);		//Wait until HSE not ready
	RST_CLK->CPU_CLOCK=0x00000003;					//HSE/2 = 12.5 MHz
	RST_CLK->PLL_CONTROL=(7<<8)|(1<<2);				//PLL CPU On;
	while((RST_CLK->CLOCK_STATUS&0x02)!=0x02);		//wait until PLL CPU not ready
	RST_CLK->PER_CLOCK|=0x08;						//EEPROM Clock enable
	EEPROM->CMD=4<<3;								//Delay = 4	 
	RST_CLK->CPU_CLOCK|=0x00000107;					//CPU Clock = 8*12.5MHz = 100 MHz
	RST_CLK->ETH_CLOCK=(1<<24)|(1<<28)|(1<<27);		//PHY_CLK_SEL = HSE, ETH_CLK_EN=1, PHY_CLK_EN=1, ETH_CLK = 25MHz
#endif	//REVISION_2

	RST_CLK->PER_CLOCK|=(1<<24)|(1<<22); 			//Enable clock for PORTD and PORTB
}

//--- Ports configuration ---
void PortConfig()
{
	PORTD->FUNC = 0x00000000;
	PORTD->ANALOG=0xFFFF;
	PORTD->RXTX=0;
	PORTD->OE|=0x7F80;
	PORTD->PWR|=0x3FFFC000;

	PORTB->FUNC = 0x00;
	PORTB->ANALOG=0x3<<14;
	PORTB->RXTX=0;
	PORTB->OE|=0x3<<14;
	PORTB->PWR|=0xF<<28;
}

#endif	//__CONFIG_C
