; generated by ARM C/C++ Compiler, 4.1 [Build 561]
; commandline ArmCC [--debug -c --asm --interleave -o.\obj\dma.o --depend=.\obj\dma.d --cpu=Cortex-M1 --apcs=interwork -O0 -I.\inc -IC:\Keil4\ARM\INC -IC:\Keil4\ARM\INC\ARM --omf_browse=.\obj\dma.crf src\DMA.c]
                          THUMB

                          AREA ||.text||, CODE, READONLY, ALIGN=2

                  DMAInit PROC
;;;11     
;;;12     void DMAInit()
000000  480e              LDR      r0,|L1.60|
;;;13     {
;;;14     	RST_CLK->PER_CLOCK|=1<<5;
000002  69c0              LDR      r0,[r0,#0x1c]
000004  2120              MOVS     r1,#0x20
000006  4308              ORRS     r0,r0,r1
000008  490c              LDR      r1,|L1.60|
00000a  61c8              STR      r0,[r1,#0x1c]
;;;15     
;;;16     	ManagementStructure[1].SourceEndPointer=UART1_BASE;							//address of register UART1->DR
00000c  480c              LDR      r0,|L1.64|
00000e  490d              LDR      r1,|L1.68|
000010  6108              STR      r0,[r1,#0x10]  ; ManagementStructure
;;;17     	ManagementStructure[1].DestinationEndPointer=(uint32_t)(&Buffer.Data[7]);	//Destination end pointer address
000012  480d              LDR      r0,|L1.72|
000014  6148              STR      r0,[r1,#0x14]
;;;18     	ManagementStructure[1].Control=0x0C000071;									//DMA cycle = 8
000016  490d              LDR      r1,|L1.76|
000018  480a              LDR      r0,|L1.68|
00001a  6181              STR      r1,[r0,#0x18]
;;;19     
;;;20     	DMA->CTRL_BASE_PTR=BASE_PTR;
00001c  480c              LDR      r0,|L1.80|
00001e  490d              LDR      r1,|L1.84|
000020  6088              STR      r0,[r1,#8]
;;;21     	DMA->CHNL_ENABLE_CLR=0xFFFFFFFF;	//disable all channel
000022  2000              MOVS     r0,#0
000024  43c0              MVNS     r0,r0
000026  62c8              STR      r0,[r1,#0x2c]
;;;22     	DMA->CHNL_REQ_MASK_SET=0xFFFFFFFF;	//disable all request
000028  6208              STR      r0,[r1,#0x20]
;;;23     	DMA->CHNL_PRI_ALT_CLR=0xFFFFFFFF;	//all channel use primary management structure
00002a  6348              STR      r0,[r1,#0x34]
;;;24     	DMA->CHNL_USEBURST_CLR=2;			//enable dma_sreq[] for UART1
00002c  2002              MOVS     r0,#2
00002e  61c8              STR      r0,[r1,#0x1c]
;;;25     	DMA->CHNL_REQ_MASK_CLR=2;			//enable dma_sreq[] for UART1
000030  6248              STR      r0,[r1,#0x24]
;;;26     	DMA->CHNL_ENABLE_SET=0x2;			//enable channel 1 for UART1
000032  6288              STR      r0,[r1,#0x28]
;;;27     
;;;28     	DMA->CFG=1;							//DMA enable
000034  2001              MOVS     r0,#1
000036  6048              STR      r0,[r1,#4]
;;;29     }
000038  4770              BX       lr
;;;30     #endif	//__DMA_C
                          ENDP

00003a  0000              DCW      0x0000
                  |L1.60|
                          DCD      0x40020000
                  |L1.64|
                          DCD      0x40030000
                  |L1.68|
                          DCD      ManagementStructure
                  |L1.72|
                          DCD      Buffer+0x7
                  |L1.76|
                          DCD      0x0c000071
                  |L1.80|
                          DCD      0x20100000
                  |L1.84|
                          DCD      0x40028000
