  Standard Peripherals Library   19868(1).

--------------------------------------------------------------------------------

v.0.5 18.01.2023

:
    1.    SpaceWire.
    2.   spw_loopback.
    3.   mdr32f8_ebc.c:
        1)   EBC_RGNx_Addr_serial_ECC()  EBC_RGNx_WSConfig()    .
        2)   EBC_RGNx_Cmd().
    4.   rlos_led     RTOS.
    5.   FPU  MPU     SVD.
    6.   DMA       .
    7.   mdr32f8_eth.h     .

:
    1.   MDR32F8_tim.h:
        1)   TIMER_EvSrc_TM1-4  TIMER_EvSrc_TMR_EVENT0-3;
        2) TIMER_EvSrc_ETR(0x8)   TIMER_EvSrc_ETR_RE(0x8)  TIMER_EvSrc_ETR_FE(0x9);
        3)        .
        4)     TIMER_CHANNEL0-3  TIMER_CHANNEL1-4.
        5)    TIMER_Prescaler  uint16_t  uint32_t.
    2.   mdr32f8_ebc.c:
        1)     xxx_CNTRL    EBC_RGNx_Init().
    3.   mdr32f8_eth.c   ETH_init()    ETH_Short_Frames_Reception.
    4.   eth_loopback   ,   .
    5.   can_transceive    readme     .
    6.   mdr32f8_adc.c:
        1)   ADC_InitStruct->ADC_SELR   ADC_Init();
        2)   .
    7.   mdr32f8_adc.h    ADCx_CONFIG1_PAUSE_NOPAUSE.
    8.   mdr32f8_eth.c   ETH_SendFrame()    (ETH_BUFFER_MODE_AUTOMATIC_CHANGE_POINTERS)   (  )     .
    9.   mdr32f8_config.h   assert_param()     mdr32f8_lib.h.
    10.   mdr32f8_milstd.c   MR_EN_Reset,    MIL_STD_1553_Cmd().
    11.   mdr32f8_can.h    CAN_STATUS_PRIOR_0.
    12.   MDR1986VE8T.h   EB_CNTR_WS_ACTIVE  EB_CNTR_WS_SETUP.
    13.   mdr32f8_clkctrl.c  CLKCTRL_DeInit()    PER0_CLK   .
    14.   mdr32f8_port.h     PORT_WriteBit().
    15.   mdr32f8_uart.h:
        1)    extern "C" {}.
        2)     UART_CLKSRC_MAX_CLK.
    16.   mdr32f8_dac.h     DAC_CLKSRC_MAX_CLK.

:
    1.   MDR32F8_tim.h   TIMER_CntMode_EvtChangeDir.
    2.   dac_dma_pingpong    DMA.
    3.   mdr32f8_eth.h     ETH_PHY_CONTROL_,      ETH_Init().
    4.   mdr32f8_adc.h    ADCx_CONFIG0_EXT_GO_SEL_ADC_GO.
    5.  mdr32f8_lib.h .
    6.   mdr32f8_arinc_rx.h, mdr32f8_can.h, mdr32f8_eth.h, mdr32f8_milstd.h, mdr32f8_ssp.h  mdr32f8_tim.h   .

--------------------------------------------------------------------------------

v.0.4.1 26/08/2020

:
    1.      BKP      LDO .

:
    1.  mdr32f8_config.h.
    2. :
        1) mdr32f8_dma.h
        2) mdr32f8_dma.c
        3) mdr32f8_tim.h
        4) mdr32f8_tim.c

--------------------------------------------------------------------------------

v.0.4 01/08/2020

:
    1.   mdr32f8_ebc.c   :
        - void EBC_RGNx_Addr_serial_ECC (uint32_t RGNx, uint32_t addr);
        - void EBC_RGNx_ECCS_Config ( uint32_t RGNx, uint32_t EBC_IT_FIX, FunctionalState NewState);
        - uint32_t EBC_RGNx_GetErrorCount (uint32_t RGNx, Cnt_type CNT);
        - __RAMFUNC void EBC_RGNx_WSConfig(uint32_t RGNx, uint32_t RGN_WS_SETUP, uint32_t RGN_WS_ACTIVE, uint32_t RGN_WS_HOLD) __attribute__((section("EXECUTABLE_MEMORY_SECTION")));
    2.   spec.c   :
        - void UNLOCK_UNIT (unit_type unit );
        - void LOCK_UNIT (unit_type unit);

:
    1.     PLL     :
        1) adc_go;
        2) eth_loopback;
        3) led_button_exti;
        4) MIL_STD_1553_valmess;
        5) rtos_led;
        6) spi_mastermode;
        7) tim_pwm.
    2.   mdr32f8_adc.h, mdr32f8_can.h, mdr32f8_dac.h, mdr32f8_eth.h, mdr32f8_ssp.h, mdr32f8_uart.h, mdr32f8_clkctrl.h, mdr32f8_tim.h     
    3.   mdr32f8_uart.h    .
    4.   mdr32f8_clkctrl.h:
        1)     Q   Q+DV   PLL;
        2)    PLL3-PLL7.
    5.   mdr32f8_ebc.h:
        1)    ;
        2)       / .
    6.   mdr32f8_port.h    .
    7.   mdr32f8_tim.h          .
    8.   mdr32f8_clkctrl.c:
        1)     ;
        2)  :
            - void CLKCTRL_HSEconfig(uint32_t CLKCTRL_HSE);
            - void CLKCTRL_CPU_PLLconfig (uint32_t PLLn, uint32_t CLKCTRL_CPU_PLLsource, uint32_t CLKCTRL_PLLn_CLK_PLLn_Q, uint32_t CLKCTRL_PLLn_CLK_PLLn_N).
    9.   mdr32f8_uart.   void UART_CLK_en(MDR_UART_TypeDef * UARTx, uint32_t UART_CLKSRC, uint32_t UART_CLK_DIV).
    10.   system_1986ve8t.c   void SystemCoreClockUpdate (void)
    11.        USE_ASSERT_INFO

--------------------------------------------------------------------------------

v.0.3 06/06/2019

:
    1.   FreeRTOS,   CAN  UART;

:
    1.     CAN  UART.
    2.   .

--------------------------------------------------------------------------------

v.0.2 20/05/2019

:
    1.   MDR1986VE8.h       :
            00000_0094     ECCAADR
            0x0000_0098     ECCDATA
            0x0000_009C     ECCECC
    2.   Startup.c:   SystemCoreClockUpdate().
    3.     mdr32f8_clkctrl.c  PLL1, PLL2.

:
    1. MDR1986VE8.h:
        1)   - S_BUS( 0x4000b000)    Cache control ; (     * ROM,RAMC,RAMD control);
        2)   SCR_Conrtol (0xe0043000));
        3)     FT_STAT0  FT_STAT1   FT_CONTROL;
        4)   RAMC_CNTR_BASE    (0x40007000);
        5)     : SPORT_PWR0-3; SPORT_PD0-3; SPORT_CL0-3.
    2.  Startup.s         .
    3.     adc_go, ARINC429_transceive, dac_dma_pingpong, eth_loopback, ext_bus_RAM ( CLKCTRL_PER0_CLKcmd(CLKCTRL_PER0_CLK_MDR_EBC_EN, ENABLE).

:
    1.   MDR1986VE8.h:
        1)   SCR_Conrtol (0xe0043000));
        2)     FT_STAT0  FT_STAT1   FT_CONTROL;
        3)   RAMC_CNTR_BASE    (0x40007000)
        4)     : SPORT_PWR0-3; SPORT_PD0-3; SPORT_CL0-3;
        5)   CRC_Control ( 0x400AF000)
        6)   ECC_BASE (0x400B0000);
        7)   CRPT_BASE (0x400AE000);
        8)   PLL3-7, CAN1-5, TIM4-5, MIL0-3, ARC0-3, EMAC0-1, SPHY1, SPW1, SPHY0-1, UART2-5, SSP1-5      ,      CLK_CNTR;
        9)    USB (0x4009D000);
        10)  TMR4 (0x4008_E000), TMR5 (0x4008_F000);
        11)  AN1 (0x4009_1000), AN2 (0x4009_2000), AN3 (0x4009_3000), AN4 (0x4009_4000);
        12)  SSP1 (0x4009_6000), SSP2 (0x4009_7000), SSP3 (0x4009_6000);
        13)  UART2 (0x4009_B000), UART3 (0x4009_C000);
        14)    UART -  ILPR (BASE_ADDR+0x020)     ;
        15)  SPW1 ( 0x4008_9000);
        16)  ETH1 (0x2101_0000);
        17)  ARINC1 RX  TX.
    2.   mdr32f8_clkctrl.c     PLL3-7, CAN1-5, TIM4-5, MIL0-3, ARC0-3, EMAC0-1, SPHY1, SPW1, SPHY0-1, UART2-5, SSP1-5;
    3.   mdr32f8_clkctrl.h    0-12  PER0_CLK;
    4.   mdr32f8_uart.c       UARTx->ILPR;
    5.  mdr32f8_arinc_rx.c   void ARINC_CLK_en(uint32_t ARINC_CLK_DIV) (     mdr32f8_arinc_rx.h);
    6.   mdr32f8_eth.c:
        1)       EMAC0_CLK;
        2)   void ETH_BRGInit(uint32_t ETH_HCLKdiv)  void ETH_ClockCMD (FunctionalState NewState);
    7.   mdr32f8_millstd.c   void MIL_STD_1553_CLK_en(MIL1553Control * MILx, uint32_t MIL_STD_1553_CLK_DIV).

--------------------------------------------------------------------------------

v.0.1
 .


